FBGA 9 X 20 Search Results

Contextual Info: Memory Product Specification DK.04GAM.F9SK2 4GB 2GB 256M x 64Bit x 2pcs Kit DDR3-2000MHz CL9 Overclocking Unbuffered DIMM Description: The overclocking unbuffered Module is a kit of two 256M x 64bit of 2GB DDR3-2000MHz CL9-9-9-27 at 1.65v Memory Module. The Module base on sixteen 128M x 8-bit DDR3 FBGA SDRAM compoments.

MT49H16M18C

Contextual Info: 16 MEG x 18, 32 MEG x 9 2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II 288Mb SIO REDUCED LATENCY RLDRAM II MT49H16M18C MT49H32M9C Features Figure 1: 144-Ball FBGA • 288Mb • 400 MHz DDR operation (800 Mb/s/pin data rate) • Organization • 16 Meg x 18, 32 Meg x 9 Separate I/O

dax6

Abstract: Mobile SDRAM
Contextual Info: V55C1256164MG 256Mbit MOBILE SDRAM 1.8 VOLT, TSOP II / FBGA PACKAGE 16M X 16 75 9 10 System Frequency fCK 133 MHz 111 MHz 100MHz Clock Cycle Time (tCK3) 7.5ns 9.0 ns 10 ns Clock Access Time (tAC3) CAS Latency = 3 6.0 ns 7.0 ns 8.0ns • Available in 54-ball FBGA (with 9x6 ball array

SMD d1c

Abstract: SMD MARKING CODE ACY qkx capacitor smd codes marking A21 MT49H16M18C
Contextual Info: ADVANCE‡ 16 MEG x 18, 32 MEG x 9 2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II 288Mb SIO REDUCED LATENCY RLDRAM II MT49H16M18C MT49H32M9C FEATURES Figure 1 144-Ball FBGA • 288Mb • 400 MHz DDR operation (800 Mb/s/pin data rate) • Organization - 16 Meg x 18, 32 Meg x 9 Separate I/O

BA5 marking

Abstract: BA7 marking plastic BA5 marking code A53 SMD Marking Code ba7 transistor SMD MARKING CODE ACY MT49H16M18C smd cod RLDRAM A22 SMD MARKING CODE
Contextual Info: 16 MEG x 18, 32 MEG x 9 2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II 288Mb SIO REDUCED LATENCY RLDRAM II MT49H16M18C MT49H32M9C Features Figure 1: 144-Ball FBGA • 288Mb • 400 MHz DDR operation (800 Mb/s/pin data rate) • Organization • 16 Meg x 18, 32 Meg x 9 Separate I/O

smd dk qk

Abstract: SMD MARKING CODE ACY smd marking codes BA5 smd marking codes BA2 RLDRAM MT49H16M18C
Contextual Info: ADVANCE‡ 16 MEG x 18, 32 MEG x 9 2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II 288Mb SIO REDUCED LATENCY RLDRAM II MT49H16M18C MT49H32M9C FEATURES Figure 1 144-Ball FBGA • 288Mb • 400 MHz DDR operation (800 Mb/s/pin data rate) • Organization - 16 Meg x 18, 32 Meg x 9 Separate I/O

MT49H16M18C

Contextual Info: PRELIMINARY‡ 16 MEG x 18, 32 MEG x 9 2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II 288Mb SIO REDUCED LATENCY RLDRAM II MT49H16M18C MT49H32M9C Features Figure 1: 144-Ball FBGA • 288Mb • 400 MHz DDR operation (800 Mb/s/pin data rate) • Organization • 16 Meg x 18, 32 Meg x 9 Separate I/O

smd marking codes BA5

Abstract: MT49H16M18C
Contextual Info: ADVANCE‡ 16 MEG x 18, 32 MEG x 9 2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II 288Mb SIO REDUCED LATENCY RLDRAM II MT49H16M18C MT49H32M9C FEATURES Figure 1 144-Ball FBGA • 288Mb • 400 MHz DDR operation (800 Mb/s/pin data rate) • Organization - 16 Meg x 18, 32 Meg x 9 Separate I/O

Contextual Info: Memory Module Specification KVR1333D3S4R9S/2GI 2GB 256M x 72-Bit PC3-10600 CL9 Registered w/Parity 240-Pin DIMM DESCRIPTION: This document describes ValueRAM's 256M x 72-bit 2GB 2048MB DDR3-1333MHz CL9 SDRAM (Synchronous DRAM) registered w/parity, (Intel Compatibility Tested), single-rank memory module, based on eighteen 256M x 4bit DDR3-1333 FBGA components. The SPD is programmed to JEDEC standard latency 1333MHz timing of 9-9-9 at

Contextual Info: Memory Module Specification KVR1333D3D8R9S/2GI 2GB 256M x 72-Bit PC3-10600 CL9 Registered w/Parity 240-Pin DIMM DESCRIPTION: This document describes ValueRAM's 256M x 72-bit 2GB 2048MB DDR3-1333 CL9 SDRAM (Synchronous DRAM), (Intel Compatibility Tested), registered w/parity, dual-rank memory module, based on eighteen 128M x 8-bit DDR31333 FBGA components. The SPD is programmed to JEDEC standard latency 1333Mhz timing of 9-9-9 at 1.5V. This

Contextual Info: Memory Module Specification KVR1333D3D8R9SL/2G 2GB 256M x 72-Bit PC3-10600 CL9 Registered w/Parity 240-Pin DIMM DESCRIPTION: This document describes ValueRAM's 256M x 72-bit 1GB 2GB 2048MB DDR3-1333 CL9 SDRAM (Synchronous DRAM) registered w/parity, dual-rank memory module, based on eighteen 128M x 8-bit DDR3-1333 FBGA components. The SPD is programmed to JEDEC standard latency 1333Mhz timing of 9-9-9 at 1.5V. This 240-pin DIMM uses

MT49H16M18

Contextual Info: ADVANCE‡ 8 MEG x 36, 16 MEG x 18, 32 MEG x 9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II 288Mb CIO REDUCED LATENCY RLDRAM II MT49H8M36 MT49H16M18 MT49H32M9 FEATURES Figure 1 144-Ball FBGA • 288Mb • 400 MHz DDR operation (800 Mb/s/pin data rate) • Organization

MT49H16M18

Contextual Info: 8 MEG x 36, 16 MEG x 18, 32 MEG x 9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II 288MB CIO REDUCED LATENCY RLDRAM II MT49H8M36 MT49H16M18 MT49H32M9 Features Figure 1: 144-Ball FBGA • 288Mb • 400 MHz DDR operation (800 Mb/s/pin data rate) • Organization

marking code a02 SMD Transistor

Abstract: transistor SMD DK MT49H16M18 smd transistor marking d1c Diode A3X transistor smd marking BA RE marking BAX smd cod plastic BA5 marking code A22 SMD MARKING CODE
Contextual Info: ADVANCE‡ 8 MEG x 36, 16 MEG x 18, 32 MEG x 9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II 288Mb CIO REDUCED LATENCY RLDRAM II MT49H8M36 MT49H16M18 MT49H32M9 FEATURES Figure 1 144-Ball FBGA • 288Mb • 400 MHz DDR operation (800 Mb/s/pin data rate) • Organization

MARKING H1 AMP

Abstract: MT49H16M18
Contextual Info: ADVANCE‡ 8 MEG x 36, 16 MEG x 18, 32 MEG x 9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II 288Mb CIO REDUCED LATENCY RLDRAM II MT49H8M36 MT49H16M18 MT49H32M9 FEATURES Figure 1 144-Ball FBGA • 288Mb • 400 MHz DDR operation (800 Mb/s/pin data rate) • Organization

MT49H16M18

Contextual Info: PRELIMINARY‡ 8 MEG x 36, 16 MEG x 18, 32 MEG x 9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II 288MB CIO REDUCED LATENCY RLDRAM II MT49H8M36 MT49H16M18 MT49H32M9 Features Figure 1: 144-Ball FBGA • 288Mb • 400 MHz DDR operation (800 Mb/s/pin data rate) • Organization

09005aef809f284b

Contextual Info: 8 MEG x 36, 16 MEG x 18, 32 MEG x 9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II 288MB CIO REDUCED LATENCY RLDRAM II MT49H8M36 MT49H16M18 MT49H32M9‡ Features Figure 1: 144-Ball FBGA • 288Mb • 400 MHz DDR operation (800 Mb/s/pin data rate) • Organization

MT49H16M18

Contextual Info: PRELIMINARY‡ 8 MEG x 36, 16 MEG x 18, 32 MEG x 9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II 288MB CIO REDUCED LATENCY RLDRAM II MT49H8M36 MT49H16M18 MT49H32M9 Features Figure 1: 144-Ball FBGA • 288Mb • 400 MHz DDR operation (800 Mb/s/pin data rate) • Organization

BW35

Contextual Info: ADVANCE‡ 4 MEG X 8, 4 MEG X 9, 2 MEG X 18, 1 MEG X 36 1.8V VDD, HSTL, DDRIIb4 SRAM 36Mb DDRII CIO SRAM 4-WORD BURST MT57W4MH8J MT57W4MH9J MT57W2MH18J MT57W1MH36J FEATURES • • • • • • • • • • • • • • • Figure 1 165-Ball FBGA

Contextual Info: ADVANCE‡ 4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb4 SRAM 36Mb QDR II SRAM 4-WORD BURST MT54W4MH8J MT54W4MH9J MT54W2MH18J MT54W1MH36J FEATURES Figure 1 165-Ball FBGA • DLL circuitry for accurate output data placement • Separate independent read and write data ports with

Contextual Info: ADVANCE‡ 4 MEG X 8, 4 MEG X 9, 2 MEG X 18, 1 MEG X 36 1.8V VDD, HSTL, DDR SIO SRAM 36Mb DDR SIO SRAM 2-WORD BURST MT57W4MH8C MT57W4MH9C MT57W2MH18C MT57W1MH36C FEATURES • • • • • • • • • • • • • • • • • Figure 1 165-Ball FBGA

Contextual Info: ADVANCE‡ 4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, DDRIIb2 SRAM 36Mb DDRII CIO SRAM 2-WORD BURST MT57W4MH8B MT57W4MH9B MT57W2MH18B MT57W1MH36B Features • • • • • • • • • • • • • • • • • Figure 1: 165-Ball FBGA

micron sram

Abstract: MT54W1MH36B MT54W2MH18B MT54W4MH8B MT54W4MH9B
Contextual Info: ADVANCE‡ 4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM 36Mb QDR II SRAM 2-WORD BURST MT54W4MH8B MT54W4MH9B MT54W2MH18B MT54W1MH36B FEATURES Figure 1 165-Ball FBGA • DLL circuitry for accurate output data placement • Separate independent read and write data ports

Contextual Info: ADVANCE‡ 4 MEG X 8, 4 MEG X 9, 2 MEG X 18, 1 MEG X 36 1.8V VDD, HSTL, DDRIIb2 SRAM 36Mb DDRII CIO SRAM 2-WORD BURST MT57W4MH8B MT57W4MH9B MT57W2MH18B MT57W1MH36B FEATURES • • • • • • • • • • • • • • • • Figure 1 165-Ball FBGA