FAIRCHILD ECL DATASHEET Search Results

Contextual Info: FAIRCHILD ECL DATASHEET • F10010 • F10016 SWITCHING CIRCUITS AND WAVEFORMS Cont'd Vcc L-) and L2 = equal length 50 Q impedance lines R j = 50 Q termination of scope CL = Jig and stray capacitance <5.0 pF Fig. 2. Decoupling 0.1 ^F from gnd to VEE and Vqq

cd4xxx

Abstract: qsc 1110 SN74ACTXXXPW 74HCxx SN74LVCxxx semiconductor cross reference M74HCXXXB1R M74HCXXXM1R SN74ACTXXXN M-SD-DT
Contextual Info: Lit. #585362-003 Fairchild Semiconductor LOGIC INDUSTRY CROSS-REFERENCE GUIDE REV. 4/2000 Visit us on the Web at www.fairchildsemi.com LOGIC INDUSTRY CROSS-REFERENCE GUIDE Family ABT AC ACT ACTQ ALS AS CD4K ECL F FAST, (FASTr) Package PDIP SOIC Wide Body SOIC

F10410

Abstract: F10410DC F10405 fairchild ECL
Contextual Info: ECL ISOPLANAR MEMORY F10410 256xl-BIT FULLY DECODED RANDOM ACCESS MEMORY FAIRCHILD VOLTAGE COMPENSATED ECL G E N E R A L D E S C R IP T IO N The F 1 041 0 is a 2 5 6 -b it R e a d /W rite Random Access M em ory, organized 256 w ord s by one bit. It has typical access tim e of 18 ns and is

F100K ECL 300 series and design guide

Abstract: AN817 6-hole Ferroxcube opti databook RADIOTRON 300-SERIES AN-817 F100311 F100K AN467
Contextual Info: Fairchild Semiconductor Application Note April 1992 Revised May 2000 Taking Advantage of ECL Minimum-Skew Clock Drivers CLOCK DISTRIBUTION BACKGROUND Among the factors affecting variability are: Digital systems have tended from their inception toward incorporation of higher speed elements rather than architectural changes as the solution to the computational

CD4010 circuit pin configuration

Abstract: ker 350 F100K SV125 0.5 mm pitch mlp 74 HC 193 n 1/fairchild tiny logic family HC/HCT series specification LVX3245 CD4000
Contextual Info: Logic Selection Guide NC7SV19 Decoder/Demultiplexer combines high speed at low voltages in MicroPak and SC70 6 Lead SC70 79 mils 2.0 mm .007 in2 4.2 mm2 49 mils 1.25 mm 35 mils 0.9 mm MicroPak 57 mils 1.45 mm 21 mils 0.55 mm .002 in2 1.45 mm2 39 mils 1 mm

F100K ECL 300 series and design guide

Abstract: F100K ECL book Amos 300-SERIES AN-817 F100K AN467 an-468 national
Contextual Info: Fairchild Semiconductor Application Note 817 June 1992 CLOCK DISTRIBUTION BACKGROUND Digital systems have tended from their inception toward incorporation of higher speed elements rather than architectural changes as the solution to the computational speed

application note 1065

Contextual Info: Fairchild Application Note 1065 February 1998 INTRODUCTION The development of the GTL technology has yielded a high performance logic family ideal for bus and backplane interface applications. GTLP, Fairchild Semiconductor’s derivative of Gunning Transceiver Logic GTL , is likely to be

CMOS TTL Logic Family Specifications

Abstract: ttl 7407 ttl to cmos converter 74c SERIES cmos logic data bi-directional switches IGBT TTL LS 7407 7407 TTL ttl 74 181 SV125 CD4010
Contextual Info: Logic SELECTION GUIDE Logic SELECTION GUIDE Fairchild Semiconductor, a long-time, leading global supplier of high performance semiconductors, offers a broad range of logic products to meet your design needs. You will not only find the performance that you

Logic Selection Guide

Abstract: voltage level translators gates BCM 7425 CMOS TTL Logic Family Specifications TTL LS 7407 TTL family CD4010 circuit pin configuration ttl to cmos converter bi-directional switches IGBT
Contextual Info: LogicGuide-08 5/28/08 10:29 AM Page 1 Logic SELECTION GUIDE LogicGuide-08 5/28/08 10:29 AM Page 2 LogicGuide-08 5/28/08 10:29 AM Page 3 Logic SELECTION GUIDE Fairchild Semiconductor, a long-time, leading global supplier of high performance semiconductors, offers

AN-1065

Contextual Info: Fairchild Semiconductor Application Note November 1996 Revised October 1998 GTLP: An Interface Technology for Bus and Backplane Applications INTRODUCTION The development of the GTL technology has yielded a high performance logic family ideal for bus and backplane interface applications. GTLP, Fairchild Semiconductor’s derivative of Gunning Transceiver Logic GTL , is likely to be

AN-1065

Abstract: GTLP16612
Contextual Info: Fairchild Semiconductor Application Note November 1996 Revised February 2001 GTLP: An Interface Technology for Bus and Backplane Applications Abstract Background The development of the Gunning Transceiver Logic GTL technology has yielded a high performance interface family

15A POWER TRANSISTOR FOR SMPS

Abstract: list of n channel power mosfet FQPF*10n20c FAN7601 detailed vfd circuit diagram for motor FAN7601 application data list of P channel power mosfet 80a charger transformer dual Phototransistor mouse FQPF10N20C
Contextual Info: New LEDs and LED Driver IC Solutions 1 • Comprehensive New Product List • New Product Highlights FAN7031, FAN7023, FAN7005 - Audio Amplifiers FIN7216-01 - Quad PHY FAN7556 - Voltage Mode PWM Controller FAN7601 - Current Mode PWM Controller FSA3357 - SP3T Analog Switch

F100K

Abstract: SY100S371 SY100S371JC SY100S371JCTR
Contextual Info: Micrel, Inc. TRIPLE 4-INPUT MULTIPLEXER WITH ENABLE SY100S371 SY100S371 DESCRIPTION FEATURES • Max. propagation delay of 1000ps ■ IEE min. of –68mA ■ Industry standard 100K ECL levels ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved

Contextual Info: Micrel, Inc. TRIPLE 4-INPUT MULTIPLEXER WITH ENABLE DESCRIPTION FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100S371 SY100S371 Max. propagation delay of 1000ps IEE min. of –68mA Industry standard 100K ECL levels Extended supply voltage option: VEE = –4.2V to –5.5V

F10016 DC

Abstract: F10010 F10016
Contextual Info: F1001 /» F10016y BCD DECADE C0UNTER/4-BIT BINARY COUNTER GENERAL DESCRIPTION — The F10010 is a high-speed synchronous, presettable. cascadable BCD Decade Counter and the F10016 is a high-speed synchronous, pre­ settable, cascadable 4-Bit Binary Counter. They are m u ltifu n ctio n MSI building

application of parity checker/generator

Abstract: F100K SY100S360 SY100S360JC SY100S360JCTR
Contextual Info: Micrel, Inc. DUAL PARITY CHECKER/ GENERATOR FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100S360 SY100S360 DESCRIPTION The SY100S360 is a dual parity checker/generator and is designed for use in high-performance ECL systems. The inputs are segmented into two groups of nine inputs each

Contextual Info: Micrel, Inc. 16-INPUT MULTIPLEXER FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100S364 SY100S364 DESCRIPTION The SY100S364 is a 16-input multiplexer designed for use in high-performance ECL systems. The four Data Select inputs S0, S1, S2, S3 determine the bit from the 16

F100K

Abstract: SY100S364 SY100S364JC SY100S364JCTR
Contextual Info: Micrel, Inc. 16-INPUT MULTIPLEXER FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100S364 SY100S364 DESCRIPTION The SY100S364 is a 16-input multiplexer designed for use in high-performance ECL systems. The four Data Select inputs S0, S1, S2, S3 determine the bit from the 16

Contextual Info: Micrel, Inc. HEX D FLIP-FLOP FEATURES DESCRIPTION Max. toggle frequency of 700MHz Clock to Q max. of 1200ps IEE min. of –98mA Industry standard 100K ECL levels Extended supply voltage option: VEE = –4.2V to –5.5V Voltage and temperature compensation for improved

AN-5013

Abstract: GTLP16612 GTLP16T1655 GTLP6C816
Contextual Info: Fairchild Semiconductor Application Note July 1999 Revised February 2001 GTLP in BTL Applications Abstract Compatibility Today’s high performance systems require fast edge rates and smooth transitions with minimal ringing, overshoot/ undershoot, and other signal integrity issues. The Gunning

F100K

Abstract: SY100S351 SY100S351JC SY100S351JCTR
Contextual Info: Micrel, Inc. HEX D FLIP-FLOP FEATURES • ■ ■ ■ ■ ■ DESCRIPTION Max. toggle frequency of 700MHz Clock to Q max. of 1200ps IEE min. of –98mA Industry standard 100K ECL levels Extended supply voltage option: VEE = –4.2V to –5.5V Voltage and temperature compensation for improved

F100K

Abstract: SY100S371 SY100S371FC SY100S371FCTR SY100S371JC ZC marking marking F24
Contextual Info: Micrel, Inc. TRIPLE 4-INPUT MULTIPLEXER WITH ENABLE SY100S371 SY100S371 DESCRIPTION FEATURES • Max. propagation delay of 1000ps ■ IEE min. of –68mA ■ Industry standard 100K ECL levels ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved

F100K

Abstract: SY100S351 SY100S351JC SY100S351JCTR
Contextual Info: SY100S351 Micrel, Inc. HEX D FLIP-FLOP FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100S351 DESCRIPTION Max. toggle frequency of 700MHz Clock to Q max. of 1200ps IEE min. of –98mA Industry standard 100K ECL levels Extended supply voltage option:

marking F24

Abstract: F100K SY100S364 SY100S364FC SY100S364FCTR SY100S364JC
Contextual Info: Micrel, Inc. 16-INPUT MULTIPLEXER FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100S364 SY100S364 DESCRIPTION The SY100S364 is a 16-input multiplexer designed for use in high-performance ECL systems. The four Data Select inputs S0, S1, S2, S3 determine the bit from the 16