CD4010 Search Results

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS097C – Revised July 2003 The CD40106B types are supplied in 14-lead hermetic dual-in-line ceramic packages F3A suffix , 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, M96,

CD40105BMS

Abstract: IOH15
Contextual Info: CD40105BMS CMOS FIFO Register December 1992 Features Description • 4 Bits x 16 Words CD40105BMS is a low-power first-in-first-out FIFO “elastic” storage register that can store 16 4-bit words. It is capable of handling input and output data at different shifting rates. This

CD4009UB

Abstract: CD4010B MS-001 MTSS001C
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS020B – Revised February 2003 The CD4009UB and CD4010B types are supplied in 16-lead hermetic dual-in-line ceramic packages F3A suffix , 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, and NSR

CD40103

Abstract: CD40102B CD40103B MS-001 MTSS001C cd40102
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS095B – Revised July 2003 The CD40102B and CD40103B types are supplied in 16-lead dual-in-line plastic packages E suffix , 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4009UB

Abstract: CD4010B MS-001 MTSS001C
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS020C − Revised October 2003 The CD4009UB and CD4010B types are supplied in 16-lead hermetic dual-in-line ceramic packages F3A suffix , 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR

CD40106B

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS097B – Revised August 2002 The CD40106B types are supplied in 14-lead hermetic dual-in-line ceramic packages F suffix , 14-lead dual-in-line plastic package (E suffix), 14-lead dual-in-line surface-mount plastic packages (M and M96

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS098D − Revised October 2003 The CD40107B is a dual 2-input NAND buffer/driver containing two independent 2-input NAND buffers with open-drain single n-channel transistor outputs. This device features a wired-OR capability and high output

SCHS097D

Abstract: CD40106B MTSS001C
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS097D – Revised September 2003 The CD40106B types are supplied in 14-lead hermetic dual-in-line ceramic packages F3A suffix , 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT,

CD40107

Abstract: CD40107BMS CD40107BF IOH15
Contextual Info: CD40107BMS CMOS Dual 2 Input NAND Buffer/Driver December 1992 Features Pinouts • High Voltage Type 20V Rating CD40107BF TOP VIEW • 32 Times Standard B Series Output Current Drive Sinking Capability - 136mA Typ. at VDD = 10V - VDS = 1V NC 1 14 VDD NC 2

mm74c14 equivalent

Abstract: cd40106bcn 0005v 74LS AN-90 C1995 CD40106B CD40106BC CD40106BM MC14584B
Contextual Info: CD40106BM CD40106BC Hex Schmitt Trigger General Description Features The CD40106B Hex Schmitt Trigger is a monolithic complementary MOS CMOS integrated circuit constructed with N and P-channel enhancement transistors The positive and negative-going threshold voltages VT a and VTb show low

CD40109BMS

Abstract: IOH15
Contextual Info: CD40109BMS S E M I C O N D U C T O R CMOS Quad Low-to-High Voltage Level Shifter December 1992 Features Description • High Voltage Type 20V Rating CD40109BMS contains four low-to-high voltage level shifting circuits. Each circuit will shift a low voltage digital logic input

Contextual Info: S E M October 1987 Revised January 1999 I C O N D U C T O R TM General Description Features The CD40106BC Hex Schmitt Trigger is a monolithic com­ plementary MOS CMOS integrated circuit constructed with N and P-channel enhancement transistors. The posi­

CD40107B

Abstract: s2444
Contextual Info: I ^ Tex a s In s t r u m e n t s C D 40107B Types Data sheet acquired from Harris S em iconductor S C H S 098 CMOS Dual 2-Input NAND Buffer/Driver High-Voltage T y p e 2 0 -V olt Rating • CD40107B is a dual 2-input NAND buffer/driver containing tw o independent 2input NAND buffers w ith open-drain single

mm74c14 equivalent

Abstract: 40106BM CD40106BCN 15VB40 CD40106
Contextual Info: CD40106BM CD40106BC Hex Schmitt Trigger General Description Features The CD40106B Hex Schmitt Trigger is a monolithic complementary MOS CMOS integrated circuit constructed with N and P-channel enhancement transistors The positive and negative-going threshold voltages VT a and VTb show low

CD4010C

Abstract: CD4010CM CD4010CN M16A MS-001 N16E
Contextual Info: Revised June 2000 CD4010C Hex Buffers Non-Inverting General Description Features The CD4010C hex buffers are monolithic complementary MOS (CMOS) integrated circuits. The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swings essentially equal to the supply voltage. This results in high noise immunity over a wide supply

CD4010B-MIL

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS020C − Revised October 2003 The CD4009UB and CD4010B types are supplied in 16-lead hermetic dual-in-line ceramic packages F3A suffix , 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR

CD4010B-MIL

Contextual Info: CD4010B-Q1 SCHS379A – MARCH 2010 – REVISED JANUARY 2012 www.ti.com CMOS HEX BUFFER/CONVERTER Check for Samples: CD4010B-Q1 FEATURES 1 • • • • • Qualified for Automotive Applications 100% Tested for Quiescent Current at 20 V Maximum Input Current of 1 µA at 18 V Over

Contextual Info: CD40109B-Q1 SCHS380 A – JUNE 2010 – REVISED AUGUST 2011 www.ti.com CMOS QUAD LOW-TO-HIGH VOLTAGE SHIFTER Check for Samples: CD40109B-Q1 FEATURES 1 • • • • • • • • • • Qualified for Automotive Applications Independent of Power Supply Sequence

real time application of D flip-flop

Abstract: CD40105BE
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS096 PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty CD40105BE ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS097D – Revised September 2003 The CD40106B types are supplied in 14-lead hermetic dual-in-line ceramic packages F3A suffix , 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT,

CD4009CN

Abstract: ci cd4009 CD4009 cd4009 B CD40xx CD4010CN CD4010C C1995 CD4009C CD4009M
Contextual Info: CD4009M CD4009C Hex Buffers Inverting CD4010M CD4010C Hex Buffers (Non-Inverting) General Description Features These hex buffers are monolithic complementary MOS (CMOS) integrated circuits The N- and P-channel enhancement mode transistors provide a symmetrical circuit with

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS098D − Revised October 2003 The CD40107B is a dual 2-input NAND buffer/driver containing two independent 2-input NAND buffers with open-drain single n-channel transistor outputs. This device features a wired-OR capability and high output

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS095A – Revised March 2002 The CD40102B and CD40103B types are supplied in 16-lead hermetic dual-in-line ceramic packages D and F suffixes , 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline package (NSR suffix),

Contextual Info: CD40102BMS CD40103BMS fS I H A R R I S S E M I C O N D U C T O R CMOS 8-Stage Presettable Synchronous Down Counters December 1992 Features Description • High Voltage Type 20V Rating CD40102BMS and CD40103BMS consist of an 8-stage syn­ chronous down counter with a single output which is active