EPT24 Search Results

MC100EPT24

Abstract: MC100EPT24D MC100EPT24DR2 MC100EPT24DT MC100EPT24DTR2 ka24
Contextual Info: EPT24 3.3VĄLVTTL/LVCMOS to Differential LVECL Translator The EPT24 is a LVTTL/LVCMOS to differential LVECL translator. Because LVECL levels and LVTTL/LVCMOS levels are used, a –3.3 V, +3.3 V and ground are required. The small outline 8–lead package and the single gate of the EPT24 makes it ideal for

MC100EPT24

Abstract: MC100EPT24D MC100EPT24DR2 MC100EPT24DT MC100EPT24DTR2
Contextual Info: EPT24 3.3V LVTTL/LVCMOS to Differential LVECL Translator The EPT24 is a LVTTL/LVCMOS to differential LVECL translator. Because LVECL levels and LVTTL/LVCMOS levels are used, a −3.3 V, +3.3 V and ground are required. The small outline 8−lead package and the single gate of the EPT24 makes it ideal for

KPT24

Abstract: MC100EPT24 MC100EPT24D MC100EPT24DR2
Contextual Info: EPT24 LVTTL/LVCMOS to Differential LVECL Translator The EPT24 is a LVTTL/LVCMOS to differential LVECL translator. Because LVECL levels and LVTTL/LVCMOS levels are used, a –3.3V, +3.3V and ground are required. The small outline 8–lead SOIC package and the single gate of the EPT24 makes it ideal

Contextual Info: EPT24 3.3VĄLVTTL/LVCMOS to Differential LVECL Translator The EPT24 is a LVTTL/LVCMOS to differential LVECL translator. Because LVECL levels and LVTTL/LVCMOS levels are used, a –3.3 V, +3.3 V and ground are required. The small outline 8–lead package and the single gate of the EPT24 makes it ideal for

KA24

Abstract: MC100EPT24 MC100EPT24D MC100EPT24DR2
Contextual Info: EPT24 3.3VĄLVTTL/LVCMOS to Differential LVECL Translator The EPT24 is a LVTTL/LVCMOS to differential LVECL translator. Because LVECL levels and LVTTL/LVCMOS levels are used, a –3.3 V, +3.3 V and ground are required. The small outline 8–lead package and the single gate of the EPT24 makes it ideal for

1030 mhz

Abstract: MC100EPT24 MC100EPT24D MC100EPT24DR2 MC100EPT24DT MC100EPT24DTR2
Contextual Info: EPT24 3.3V LVTTL/LVCMOS to Differential LVECL Translator The EPT24 is a LVTTL/LVCMOS to differential LVECL translator. Because LVECL levels and LVTTL/LVCMOS levels are used, a −3.3 V, +3.3 V and ground are required. The small outline 8−lead package and the single gate of the EPT24 makes it ideal for

MC100EPT24

Abstract: KPT24
Contextual Info: EPT24 3.3V LVTTL/LVCMOS to Differential LVECL Translator Description The EPT24 is a LVTTL/LVCMOS to differential LVECL translator. Because LVECL levels and LVTTL/LVCMOS levels are used, a −3.3 V, +3.3 V and ground are required. The small outline

motorola HEP cross reference

Abstract: EPT 4045 KPT23 motorola HEP 320 cross reference vef 202 manual KEP52 MC10EP016 HEP 801 hep51 HEP64
Contextual Info: BR1513/D Rev. 2, Apr-2001 ECLinPS Plus Device Data ECLinPS Plus Device Data Advanced ECL in Picoseconds BR1513/D Rev. 2, Apr–2001  SCILLC, 2001 Previous Edition  2000 “All Rights Reserved” ECLinPS, ECLinPS Lite, and ECLinPS Plus are trademarks of Semiconductor Components Industries, LLC.

el90

Abstract: H352 DL122 DL140 ept20 EPT25 LVEL92 EPT22 H124 ttl databook
Contextual Info: AN1672/D The ECL Translator Guide ECL • TTL • PECL • LVECL • LVPECL • CMOS • LVTTL How To Make Them Talk To Each Other http://onsemi.com Prepared by: Paul Shockman, Paul Hunt ON Semiconductor Logic Applications Engineering APPLICATION NOTE Translation between ECL signals off different power

MC100EPT24

Contextual Info: EPT24 3.3V LVTTL/LVCMOS to Differential LVECL Translator Description The EPT24 is a LVTTL/LVCMOS to differential LVECL translator. Because LVECL levels and LVTTL/LVCMOS levels are used, a −3.3 V, +3.3 V and ground are required. The small outline

H124

Abstract: LVEL17 MC10EPT20
Contextual Info: AN1672/D The ECL Translator Guide PECL • LVPECL • NECL • TTL • LVTTL/LVCMOS • CMOS Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering APPLICATION NOTE Objective This application note is intended to provide the basic device selection and connection information to enable signal

MC100EPT24

Contextual Info: EPT24 3.3V LVTTL/LVCMOS to Differential LVECL Translator Description The EPT24 is a LVTTL/LVCMOS to differential LVECL translator. Because LVECL levels and LVTTL/LVCMOS levels are used, a −3.3 V, +3.3 V and ground are required. The small outline

MC10EPT25

Abstract: MC10EPT22 MC10EPT24 MC10EPT23 MC10EPT21 ttl 7709 AND8072 HCT CMOS family characteristics AN1568 AND8020
Contextual Info: AN1672/D The ECL Translator Guide PECL • LVPECL • NECL • TTL • LVTTL/LVCMOS • CMOS http://onsemi.com Prepared by: Paul Shockman ON Semiconductor APPLICATION NOTE Objective receiver in the LOW state. In contrast, ECL drivers source current in both HIGH and LOW states to the receiver).

a1020 pnp

Contextual Info: EPT24 3.3V LVTTL/LVCMOS to Differential LVECL Translator Description The EPT24 is a LVTTL/LVCMOS to differential LVECL translator. Because LVECL levels and LVTTL/LVCMOS levels are used, a −3.3 V, +3.3 V and ground are required. The small outline

MC100EPT24

Abstract: MC100EPT24D EPT24
Contextual Info: MOTOROLA Order Number: EPT24/D Rev. 0.1, 05/1999 Semiconductor Components EPT24 SO–8, D SUFFIX 8–LEAD PLASTIC SOIC PACKAGE CASE 751 ORDERING INFORMATION EPT24D SOIC Product Preview LVTTL/LVCMOS to PIN DESCRIPTION Differential LVECL Translator

EL90

Abstract: AN1568 AND8020 AND8066 AND8072 MC10EP195 H124 MC10EPT22 MC10EPT20
Contextual Info: AN1672/D The ECL Translator Guide PECL • LVPECL • NECL • TTL • LVTTL/LVCMOS • CMOS http://onsemi.com Prepared by: Paul Shockman ON Semiconductor APPLICATION NOTE Objective This application note is intended to provide the basic device selection and connection information to enable signal

ELT24

Abstract: AN1568 AND8020 AND8066 AND8072 MC10EP195 H124 MC10EPT22 MC10EPT20
Contextual Info: AN1672/D The ECL Translator Guide PECL • LVPECL • NECL • TTL • LVTTL/LVCMOS • CMOS http://onsemi.com Prepared by: Paul Shockman ON Semiconductor APPLICATION NOTE Objective This application note is intended to provide the basic device selection and connection information to enable signal