ECL TO TTL CONVERTER Search Results

Contextual Info: 100324 100324 Low Power Hex TTL-to-ECL Translator Literature Number: SNOS128A 100324 Low Power Hex TTL-to-ECL Translator General Description Features The 100324 is a hex translator, designed to convert TTL logic levels to 100K ECL logic levels. The inputs are compatible

Contextual Info: DP8480A DP8480A 10k ECL to TTL Level Translator with Latch Literature Number: SNOSBN8A DP8480A 10k ECL to TTL Level Translator with Latch General Description Features This circuit translates ECL input levels to TTL output levels and provides a fall-through latch The TRI-STATE outputs

Contextual Info: DP8482A DP8482A 100k ECL to TTL Level Translator with Latch Literature Number: SNOSBO0A DP8482A 100k ECL to TTL Level Translator with Latch General Description Features This circuit translates ECL input levels to TTL output levels and provides a fall-through latch The TRI-STATE outputs

DP8481

Contextual Info: DP8481 DP8481 TTL to 10k ECL Level Translator with Latch Literature Number: SNOSBN9A DP8481 TTL to 10k ECL Level Translator with Latch General Description Features This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with

Contextual Info: DP8483 DP8483 TTL to 100k ECL Level Translator with Latch Literature Number: SNOSBO1A DP8483 TTL to 100k ECL Level Translator with Latch General Description Features This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with

Contextual Info: 100329 100329 Low Power Octal ECL/TTL Bidirectional Translator with Register Literature Number: SNOS122A 100329 Low Power Octal ECL/TTL Bidirectional Translator with Register General Description The 100329 is an octal registered bidirectional translator designed to convert TTL logic levels to 100K ECL logic levels

Contextual Info: 100325 100325 Low Power Hex ECL-to-TTL Translator Literature Number: SNOS129A 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex translator for converting F100K logic levels to TTL logic levels. Differential inputs allow each circuit

F100K

Abstract: J24E W24B 100124
Contextual Info: 100324 Low Power Hex TTL-to-ECL Translator General Description Features The 100324 is a hex translator, designed to convert TTL logic levels to 100K ECL logic levels. The inputs are compatible with standard or Schottky TTL. A common Enable E , when LOW, holds all inverting outputs HIGH and holds all true outputs LOW. The differential outputs allow each circuit to be

Q20P010

Abstract: Q20M100 carry look ahead adder Q20080 Q20P025 Q20025 vernier Q20000 Q20004 Q20010
Contextual Info: D EV IC E SP EC IFIC A TIO N LOGIC ARRAYS Q20000 “TURBO” ECL/TTL Q20000 FEATURES Figure 6. Q20080 Die • • • • • • • • • • Up to 18,777 gates, channelless architecture 100 ps equivalent gate delays Low power 0.5-1.0 mW/gate 10K, 10KH, 10OK ECL and mixed ECL/TTL capability

CLGA

Abstract: ECL 100124
Contextual Info: OBSOLETE 100324 www.ti.com SNOS128B – AUGUST 1998 – REVISED APRIL 2013 100324 Low Power Hex TTL-to-ECL Translator Check for Samples: 100324 FEATURES DESCRIPTION • • • • • • • The 100324 is a hex translator, designed to convert TTL logic levels to 100K ECL logic levels. The inputs

Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

SN100KT5574

Abstract: SN100KT5574DW SN100KT5574NT
Contextual Info: SN100KT5574 OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS SDZS009 – D3418, JANUARY 1990 • • • • • DW OR NT PACKAGE TOP VIEW 100K Compatible ECL Clock and TTL Control Inputs Flow-Through Architecture Optimizes PCB

Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

SN10KHT5578

Abstract: SN10KHT5578DW SN10KHT5578DWR SN10KHT5578NT
Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

SN10KHT5578

Abstract: SN10KHT5578DW SN10KHT5578DWR SN10KHT5578NT SN10KHT5578NTE4 sn10kht55
Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

Contextual Info: SN10KHT5574 OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS SDZS010 – JANUARY 1990 – REVISED OCTOBER 1990 • • • • • DW OR NT PACKAGE TOP VIEW 10KH Compatible ECL Clock and TTL Control Inputs 1Q 2Q 3Q 4Q