ECL D FLIP FLOP Search Results

T flip flop IC

Abstract: Toggle flip flop IC T Flip-Flop D flip flop IC ECL D flip flop 12 V T flip flop IC R S Flip Flop Latch MC100ES6030 MC100ES6030DW MC100ES6030DWR2
Contextual Info: MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Order Number: MC100ES6030 Rev 0, 10/2003 DATA SHEET Preliminary Information 2.5/3.3V ECL DTriple D with Flip- Flop 2.5/3.3V ECL Triple Flip-Flop Set and Reset with Set and Reset MC100ES6030

100131F

Abstract: 100131Y
Contextual Info: 100131 Signetics Flip-Flop Triple D-Type M aster-Slave Flip-Flop Product Specification ECL Products DESCRIPTION 100131 has three D-type flip-flops, with direct and output, separate clock, set addition, all three flip-flops mon clock, set and reset. master-slave

SN100KT5578

Contextual Info: SN100KT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE _ D3485. APRIL 1990-REVISED OCTOBER 1990 * 100K Compatible * TTL Clock and ECL Control Inputs * Noninverting Outputs *

Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

SN10KHT5578

Abstract: SN10KHT5578DW SN10KHT5578DWR
Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

Texas Instruments TTL Logic

Abstract: Texas Instruments TTL
Contextual Info: SN10KHT5576, SN100KT5576 OCTAL ECL-TO-TTL TRANSLATORS WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS D3603. JU LY 1990 DW OR NT PACKAGE TOP VIEW ECL and TTL Control Inputs

Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

SN10KHT5578

Abstract: SN10KHT5578DW SN10KHT5578DWR SN10KHT5578NT
Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

SN10KHT5578

Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

SN10KHT5578

Abstract: SN10KHT5578DW SN10KHT5578DWR SN10KHT5578NT SN10KHT5578NTE4 sn10kht55
Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

ECL 100151

Abstract: 100151 PM710 100151F 100151Y
Contextual Info: Signetics 100151 Flip-Flop Hex D-Type Master-Slave Flip-Flop Product Specification ECL Products DESCRIPTION The 100151 contains six flip-flops with complement and data outputs, a master reset MR and a pair of common clock inputs. Data enter the flip-flop on the

SN10KHT5578

Abstract: D3484
Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE D3484. A P R IL 1990 DW OR NT PACKAGE 10KH Compatible TOP VIEW TTL Clock and ECL Control Inputs

F100K

Abstract: SY100S331 SY100S331JC SY100S331JCTR
Contextual Info: Micrel, Inc. TRIPLE D FLIP-FLOP FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTION The SY100S331 offers three D-type, edge-triggered master/ slave flip-flops with true and complement outputs, designed for use in high-performance ECL systems. Each flip-flop is

LA 6348

Abstract: 10231F 10231N 10231
Contextual Info: Signetics 10231 Flip-Flop Dual D-Type Master-Slave Flip-Flop High-Speed Product Specification ECL Products DESCRIPTION The 10231 is a High-Speed Dual D-type Master-Slave Flip-Flop. It contains Asyn­ chronous Set (S) and Reset (R) which override Clock (CP) and Clock Enable

analog multimeter

Abstract: Metrawatt AN948 APP948 HP16500C MAX101A MAX101AEVKIT MAX104
Contextual Info: Maxim > App Notes > A/D and D/A CONVERSION/SAMPLING CIRCUITS HIGH-SPEED SIGNAL PROCESSING Keywords: data acquisition system, analog to digital converter, ADC, flash, time-interleaved quantizer, ECL-toTTL level shifters, ECL termination, FR4, FIFO, memory, flip-flop, register, FPGA, RAM

ECL 10131

Abstract: signetics 10131 10131dc 10131N 10131F 25CC C30C62
Contextual Info: S ignetics 10131 Flip-Flop Dual D-Type Master-Slave Flip-Flop Product Specification ECL Products DESCRIPTION The 10131 is a Dual Master-Slave Flip­ Flop. Each flip-flop can be clocked sepa­ rately by holding the common Clock in the LOW state and using the Clock