ECL 10124 Search Results

10124N

Abstract: 10K ECL 10124F WF-130 ecl 10124 ecl 10K signetics 10124
Contextual Info: 10124 Signetics Translator Quad TTL-to-ECL Translator Product Specification ECL Products DESCRIPTION The 10124 is a Quad T T L - ECL Trans­ lator with an individual Data and a com­ mon Select TTL-compatable input on each gate. When the Select input is in

kd 616

Abstract: ana 650 SP10115 SP10116 SP10124 SP1012
Contextual Info: S P 10124 PLESSEY ECL 10,000 SERIES SEMICONDUCTORS SP10124 Q U A D T T L T O ECL TRANSLATOR P O S IT IV E LO G IC The SP1012 4 is a quad translator fo r interfacing data and control signals between a saturated log ic section and the ECL section o f dig ita l systems. The SP10124

HD10125

Contextual Info: H D 10124 Quadruple T T L to ECL T ra n s la to rs The HD10124 is a quad translator fo r interfacing data and co n tro l signals between a saturated logic section and the ECL section o f digital systems. The device has T T L com patible inputs, and ECL com plem entary open-em itter outputs th a t allow

10124N

Abstract: 10124D 10124F 10124DC
Contextual Info: Philips Components 10124 Document No. 8 5 3 -0 6 5 7 ECN No. 99799 Date of Issue June 14, 1990 Status Product Specification Translator Quad TTL-to-ECL Translator ECL Products FEATURES ORDERING INFORMATION • Typical propagation delay: 3.5ns • Typical supply current -lEE : 53mA

ay-5-1012

Abstract: ali m 3329 PROCESSOR ALI 3329 ali 3329 b ali 3329 SN74188 sn74s188 str 52100 SN7452 replacement of bel 187 transistor
Contextual Info: GENERAL INFORMATION lie of Contents • Alphanumeric Index • Selection Guides • Glossary INTERCHANGEABiliTY GUIDE MOS MEMORIES TTL MEMORIES ECl MEMORIES MICROPROCESSOR SUMMARY 38510/MACH IV PROCUREMENT SPECIFICATION JAN Mll-M-38510 INTEGRATED CIRCUITS

10124N

Contextual Info: Philips Components-Signetics 10124 Docum ent No. 8 5 3 -0 6 5 7 E C N No. 99799 D ate of Issue June 14, 1990 Status Product Specification Translator Quad TTL-to-ECL Translator E C L Products ORDERING INFORMATION FEATURES DESCRIPTION ORDER CODE 16-Pin Plastic DIP

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quad TTL to MECL Translator M C I 012 4 The M C 10124 is a quad translator tor interfacing data and control signals between a saturated logic section and the M ECL section ot digital systems. The M C 10124 has TTL compatible inputs, and M EC L complementary open-em itter

HD10124

Abstract: HD10125
Contextual Info: H D 10124 Q uadruple T T L to ECL T ra n s la to rs The H D 1 0 1 2 4 is a quad translator fo r interfacing Power supply requirements are ground, + 5 .0 V , and data and control signals between a saturated logic section and the E C L section of digital systems.

TTL RS232 buffer

Abstract: 9582 Fairchild 9582 ECL 10524 UA1489A 11C24 11C44 8T13 8T14 8T23
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-ECL E16 95124/10124/10524 E15 9595 E14 100123 11 7 ( 10) eJ?i •=0 = 3 ;^ (3) (16) 1 4 (2) 1 3 (1) (15) Vcc = Pin 5 Vcca = Pin 6 Vee = Pin 12 GND = Pin 4 V cc = Pin 9 (6) V ee = Pin 21 (18) ( ) = DIP E17 10125/10525

t25 dc he nv

Contextual Info: ECL PRODUCT INFORMATION Test Voltage Values V v ih a MIN Vil a MAX -30 °C +25°C +85°C -0.890 -0.810 -0.700 -1.890 -1.850 -1.825 -1.205 -1.105 -1.035 -1.500 -1.475 -1.440 PARAMETER LOW LEVEL OUTPUT VOLTAGE LOW LEVEL VOH (V) HIGH LEVEL V0 LA <V> THRE8HOLD

Contextual Info: H D 10124 Quadruple T T L to ECL T ra n s la to rs The HD10124 is a quad translator for interfacing data and control signals between a saturated logic section and the E C L section of digital systems. The device has T T L compatible inputs, and E C L complementary open-emitter outputs that allow

signetics 10107

Abstract: decoder active high outputs signetics 10131 ECL 10131 ECL 10102 ECL 10105
Contextual Info: LANSDALE SEMICONDUCTOR bOE J> I 5 3 ^ 3 0 3 O O O Q S m 0^3 « L T E Rating Supply Voltage - Vcc Input Voltage - Vjn SIGNETICS INTEGRATED CIRCUITS Output Source Current 10K ECL Storage Temperature Range Emitter-coupled logic is the fastest logic technology available

74LS244 PIN diagram

Abstract: 10524 74LS244 74LS244 diagram 11C24 11C44 74LS240 74LS241 74LS540 74LS541
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-ECL E16 95124/10124/10524 E15 9595 E14 100123 5 (11)7 ( 10) • = 0 = 3 3 (7) eJ?i 2 (6) ¡ 7 = 0 ^ : 4 (8) (3) ; ^ 0 = ^ 5(16) (14) 1 4 (2) 1 3 (1) (15) Vcc = Pin 5 V cc a = Pin 6 V ee = Pin 12 G N D = Pin 4 V cc = Pin 9 (6)

11C44

Abstract: 11C58 E106 10125 ecl to ttl 11C24 10124 fairchild mos
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-ECL E15 9595 E14 100123 E16 95124/10124/10524 5 (1 1 ) 7 (10) • = 0 = 3 3 (7) eJ?i ¡7 = 0 ^ : 2(6) 4 (8) ;^ 0=^5 (3) (16) (14) 1 4 (2) 1 3 (1) (15) Vcc = Pin 5 V cc a = Pin 6 V ee = Pin 12 G N D = Pin 4 V cc = Pin 9 (6)

E106

Abstract: s19112 e104 m 9625 11C24 11C44 11C58 11C83 E105 E107
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-ECL E104 11C83 M 3 — •"- R 4 CP - E105 10192/10592 Q • 10 6 - V r e f V cc = Pin 1 V c c a = Pin 14 G N D = Pin 7 V cc = Pin 16 4 V ee = Pin 8 (12) ( ) = Flatpak E106 10177/10577 E107 100181 (MSB)

Contextual Info: FAIRCHILD INTERFACE LEVEL TRANSLATORS Power Dissipation mW Logic/Connection Diagram s 00 (+V)-2 0 +0 4 90 440 G12 6A Dual ECL-TTL +5 0 -5 2 +2 4 +0 4 60 375 E15 6B +5 0 0 0 to -30 Vtap-1 0 (-V)+2 0 DEVICE NO.(1,2) +12 to +20 Item Supply Voltage V- (Typ)

74 TTL PACKAGE OUTLINES

Abstract: 75451ATC 1606B 55451A 75451ARC
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0 .0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V - 2 .0 0.4 90 440 TO-86 6A.9A 9595* Dual ECL-TTL Translator +5.0 - 5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

75450apc

Abstract: 10125 ecl to ttl fairchild 9112 7S45 pin diagram for all 74 series ttl gates
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0 .0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V - 2 . 0 0.4 90 440 TO-86 6A.9A 9 5 9 5 * Dual ECL-TTL Translator +5.0 - 5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver

75451

Abstract: 55450B 75452B fairchild 9112
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 95 9 5 * Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

cc770

Abstract: AMCC Q700
Contextual Info: Q /ï^ c j 004958 G/n C. DEVICE SPECIFICATION APPLIED M IC R O C IR C U IT S C O R PORATION Q700 SERIES ECL/TTL LOGIC ARRAYS FEATURES VARIOUS ARRAY SIZES 250, 500, 1000 equivalent gate versions to support various circuit requirements. VERY HIGH SPEED 0.5 to 0.9 ns average gate delay within the internal array.

75452

Abstract: 55450B
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 9595* Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

fairchild ECL

Abstract: 75453btc 55450B 754S3B
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 95 9 5 * Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

9582 Fairchild

Abstract: 95H28 11C44 11C58 11C24 95H29 E106 MOS Clock Driver 9582 95H28 Fairchild
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-ECL E21 11C58 E22 9582 E23 95115/10115/10515 9 5 (8)4 cx 1 1 - .¡¿ .1 4 2 Q Vex INPUT FILTER — (14) 10 ( 13)9 7 (11) 6 (10) (16) 12 ( 1) 13 15 (3) 14 (2) 14 BIAS FILTER 12 13 13 3 (7) 2 (6) U 0 -6 11 (15)

Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 95 9 5 * Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21