106XX Search Results

11R11R

Abstract: M20-106XX00
Contextual Info: Customer nformation Shee DRAWING No., M20-106XX00 SH EET 2 OF 2 | IF IN DOUBT ASK TTTT NOT TO SCALE THIRD ANGLE PROJECTION A L L DIMENSIONS IN mm ORDER CODE: M20-106XX00 •2.54 X No. OF PITCHES ±0.20- No. OF WAYS 01 TO 12 SPECIFICATIONS: ELECTRICAL: CURRENT RATING - 3A AC/DC

36p15

Abstract: 101XX-6000XX 10220-L8A9 14p marking MDR connector 102XX-02 sumitomo 3m mdr MDR 26 102XX 103XX-52X0-XXX
Contextual Info: JNPS- 0135D 製 品 仕 様 書 Product Specification ３Ｍ 印 ＭＤＲ ノンシールドシェルストレートタイプ キット 103XX-42X0-XXX 103XX-52X0-XXX 部品 106XX-4200-XXX 106XX-5200-XXX 3342-XX １０６００－L0F0-X 3M Brand MDR Non-Shielded Shell Straight Type

Z20-320

Abstract: M20-11800XX
Contextual Info: Customer Information Shee SHEET 2 OF 2 DRAWING No.! M20-11800XX J! T T IF IN DOUBT - ASK THIRD ANGLE PROJECTION NOT TO SCALE A LL DIMENSIONS IN mm NOTES; 1, TO BE USED WITH CRIMP MOULDINGS M20-106XX00 AND M 20-107XX00 SPECIFICATIONS SHOWN BELOW APPLY WHEN

MDR connector

Abstract: sumitomo 3m mdr JNPS-0173 14p marking M26x30 102XX-52XX marking 2u 3U-0010-0935-7 102XX-62XXXX 10220-L8A9
Contextual Info: JNPS- 0135D 製 品 仕 様 書 Product Specification ３Ｍ 印 ＭＤＲ ノンシールドシェルストレートタイプ キット 103XX-42X0-XXX 103XX-52X0-XXX 部品 106XX-4200-XXX 106XX-5200-XXX 3342-XX １０６００－L0F0-X 3M Brand MDR Non-Shielded Shell Straight Type

ALU of 4 bit adder and subtractor

Abstract: 4 bit ALU binary 4 bit subtractor 4068B 8 bit subtractor 4011B 4023B 4bit alu 40688 cmos 95H55
Contextual Info: FA IR C H ILD D IG ITA L ECL Logic/Connection Diagram 4.6 485 E58 'S Xfc Package s * c Power Dissipation mW (Typ) DEVICE NO.* c o o e 3 u. Item No. of Input Bits A R ITH M E TIC OPERATORS 1 Adder/S ubtractor 95H84 2 Dual A dder/S ubtractor 10180/10580 2x2

32 line demux

Abstract: 5 to 32 demux logic diagram of dual 2 to 4 decoder E112 Decoder 5 to 32
Contextual Info: FAIR C H ILD DIG ITA L ECL 2 T rip le M u ltip le x e r 100171 1 3 3 1.7 3 T rip le M u ltip le x e r 9580 1 3 3.2 Function Item 1 D ual M u ltip le x e r 2.0 3.0 210 2.0 0.8 360 3.2 2.6 300 2.6 260 50 f l Line E50 6B 2.5 200 50 n Line E98 4L,6B ,9B 220 50 f l Line

10171

Abstract: 10558 demux pin diagram E112 32 line demux multiplexer 8 2*1
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-ECL E11 10172/10572 E10 10171/10571 3 (2) (6) 15 14 2 (3) 15 (2) 14 < 1 1 )7 - (13)8 13 12 11 10 6 5 4 3 (1) (16) (15) (14) (10) (9) (8) (7) <1) (16)05) (14) (10) (9) (8) (7) VCC1 = Pin 1 (5 ) VCC2 = Pin 16 (4)

95H04

Abstract: 11C01 95H02 95H03 95H22 95H23 95H24 95L22 95L23 95L24
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-ECL E97 100164 E96 10100/10500 22 {23)(24) ( 1) (2) (3) (4) (5) (9 ) ( 10)(11)(12)(13)(14)(15) ( 16) 1 2 3 4 5 6 7 8 12 13 14 15 16 17 18 19 ( 8) Vcc = Pin 9 (6) VCCA = Pin 10 ( 7 ) Vee = Pin 21 (18) ( -) = DIP

95H02

Abstract: Q302 95H00 95H04 95H24 95L24 95H22 95H03 10507 10107 fairchild
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-ECL E64 95000/10000 E63 95H00 9 11 13 14 i CPPE Po Pi P2 9 5 15 P3 (1 ) ,"3D| dsm r 16 Qo Q i 02 7 6 3 03 2 ( 10)6 - (1)13 (10)6 (15)11 (13)9 (15)11 ^ (11)7 j(14) 10j PE CP (8) E65 10141/10541 Po P1 P2 P3

h 9645

Abstract: Level Translators 9644 10125 ecl to ttl B1 9A 9645 fairchild Quad TTL to MOS Driver 8T26 11C44 11C58
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS INTERFACE RECEIVER ENABLE RECEIVER O UT A DRIVER IN C DRIVER IN C 155 9641/26S11 Vcc G ND ^ 14 RECEIVER □ 0UTD TJ IND “ I DRIVER 3 STROBE BUS D RECEIVER OUT D H DRIVER IND ^ STROBE ^ BUS C ^ 1 DRIVER i” 1 RECEIVER

74LS240

Abstract: 75108 74LS244 74S140 74LS241 74LS540 74LS541 E105
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS INTERFACE I8 9622 17 9621 19 9624 GND [ I 2 Nc Q 3 IN A l C 4 IN A 2 ^ 5 IN A3 Q 6 IN A O Q 7 Vd d L f t •14 □ vcc 13 □ tap 12 □ nc 11 □ in B3 10 J in B2 9 □ in B1 8 □ OUT B 112 9650 110 111 9625 9627 1 GND

11C01

Abstract: 95H02 95H03 95H04 95H22 95H23 95H24 95L22 95L23 95L24
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DJGITAL-ECL E8S 10117/10517 E84 10113/10513 8 4. (9)5 — & P M -^ E86 10118/10518 •2 (8 ) -3 * (7) (11)7 (11)7 (13)9. ■.an ix g ; (14)10 (15)11 (14)10 (15) VCC1 = Pin 1 (5) V cc 2 = Pin 16 (4) Vee = Pin 8 (12) ( ) = Flatpak

l0610

Abstract: 93S43 93S62 D114 D115 D116 D117 D118 4 bit parity generator
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DJGITAL-ECL E8S 10117/10517 E84 10113/10513 8 4. & P M - (9)5 — ^ E86 10118/10518 •2 (8 ) -3 * (7) (11)7 (11)7 (13)9. ■.an (14)10 (15)11 (14)10 (15) (16)12(1)13- VCC1 = Pin 1 (5) V cc 2 = Pin 16 (4) Vee = Pin 8 (12)

10107 fairchild

Abstract: 11C01 95H02 95H03 95H04 95H22 95H23 95H24 95L22 95L24
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-ECL E92 100117 E91 100107 E90 100102 8 5 16 ( 13) ( 14) 17 ( 15) 18( 16) 19( 17) 20 - 1 5 ( 12) :i r : 13 ( 10) 14 ( 11 ) 1 2 ( 9) ( 20 ) 23 ( 21 ) 24 - 11 ( 8 ) cx; 8 ( 5) (22)1 ( 23 ) 2 7 ( 4) 5 ( 2) ( 24) 3

Contextual Info: FAIRCHILD INTERFACE LEVEL TRANSLATORS Power Dissipation mW Logic/Connection Diagram s +12 to +20 0.0 (+VJ-2.0 +0.4 90 440 G12 6A Dual ECL-TTL +5.0 -5.2 +2.4 +0.4 6.0 375 E15 6B TTL-MOS +5.0 0.0 to -30 Vtap -1-0 <-V)+2.0 z o > UJ Û 1 9112 TTL-H LD TL Hex

Contextual Info: FAIRCHILD INTERFACE LEVEL TRANSLATORS Power Dissipation mW Logic/Connection Diagram s 00 (+V)-2 0 +0 4 90 440 G12 6A Dual ECL-TTL +5 0 -5 2 +2 4 +0 4 60 375 E15 6B +5 0 0 0 to -30 Vtap-1 0 (-V)+2 0 DEVICE NO.(1,2) +12 to +20 Item Supply Voltage V- (Typ)

95H90

Abstract: 95h90 prescaler 95H16
Contextual Info: FAIRCHILD DIGITAL ECL Parallel Entry No. of Bits Max Clock Freq. MHz Typ Clock To Output Delay-ns (Typ) Power Dissipation mW (Typ) Logic/Connection Diagram 95H00 4 D 4S 150 3,2 395 E63 6B 2 4-B it S hift Register 95000 4 D 4S 200 3.2 345 E64 6B 3 4-Bit Shift Register

9582 ECL

Contextual Info: FAIRCHILD INTERFACE LINE DRIVERS/RECEIVERS/TRANSCEIVERS Drivers per Package Logic/Connection Diagram s Package(s) 4 I49 6A.9A 10 +5 0 108 4 D2 3I, 6A,9A 48 13 +5 0 98 4 D2 3I, 6A,9A Single Ended 48 11 +5 0 52 2 D5 3I, 6A.9A Volt Single Ended 48 70 +5 0 88

NOR Gates

Abstract: 95H23 10107 fairchild 10502 95101 95H03 11C01 95H02 95H04 95H22
Contextual Info: FA IR C H ILD DIG ITAL ECL SSI F U N C TIO N S Item C o n t’d Function D EV IC E NO .* tpd ns (Typ) Power Dissipation mW (Typ) Logic/ Connection Diagram Package(s) NO R Gates (C on t’d) 1 T rip le NOR 95106 2.0 75 E78 6B 2 T rip le NOR 10106/10506 2.0

95h28

Abstract: e74 330 330 e74 ecl 9528 d flipflop dual d flip-flop oa 9505 D Flipflop 95h28 oa9505 11C06
Contextual Info: FA IR C H ILD D IG ITA L ECL SSI F U N C TIO N S Item Cont'd Function D EV IC E N O .* tpd ns (Typ) Power Dissipation mW (Typ) Logic/ Connection Diagram Package(s) O R /N O R Gates (C o n t’d) 1 Q uad O R /N O R 10101/10501 2.0 100 E74 4L,6B,9B 2 Q u in t O R /N O R

Contextual Info: Rosenberger LWL-Technik Fiber Optic Inserts according to DIN 41626-3 Steckverbindereinsatze nach DIN 41626-3 - Einzelkontakt in Verbindung mit Kontakttragern wie Stecker-, Mischleisten Oder Vielfachsteckern z. B. D-Sub Trapezleiste, Mischleiste DIN 41612

Contextual Info: DRAWING No.: Customer Information Sheet I M 8 0 - 8 8 1XXXX SHEET 2 OF 2[ IF IN D O U B T - ASK | c | NOT TO SCALE RECOMMENDED •DIM — MAX + DIM + PCB THIRD ANGLE PROJECTION LAYOUT MAX - 'A' — + + 3) 0 0 . 9 0 MIN TYP STRAIN RELIEF STRAP HOLES (OPTIONAL)

95H28 Fairchild

Abstract: dual d flip-flop 95H28
Contextual Info: FAIRCHILD DIGITAL ECL SSI FUNCTIONS Item Cont'd Function Power Dissipation mW (Typ) Logic/ Connection Diagram Package(s) DEVICE NO.* *pd ns (Typ) 10101/10501 2.0 100 E74 4L,6B,9B 230 E90 4Q,6Q OR/NOR Gates (Cont’d) 1 Quad OR/NOR 2 Q uint OR/NOR 100102

74LS244 PIN diagram

Abstract: 74LS244 e104 11C83 74LS240 74LS241 74S140 E105 E106 E107
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-ECL E104 11C83 M 3 — •"- R 4 CP - E105 10192/10592 Q • 10 6 - V r e f V cc = Pin 1 V c c a = Pin 14 G N D = Pin 7 V cc = Pin 16 4 V ee = Pin 8 (12) ( ) = Flatpak E106 10177/10577 E107 100181 (MSB)