DV74H Search Results

Contextual Info: AVG DDi Semiconductors Technical Data A vailable Q2, 1995 DV74HC533 DV74HCT533 Octal 3-State Inverting Transparent Latch The latches in this device appear transparent to data i.e., the outputs change asynchronously when Latch Enable is High. When Latch Enable is Low, data meeting the set-up and hold

Contextual Info: AVG Semiconductors DDi Technical Data DV74HC221 Dual Non-Retriggerable Monostable Multivibrator This device is pin compatable with the DV74XX123. Unlike DV74XX123, the HC221 is non-retriggerable. It has output control by three methods. The basic pulse time is programmed

Contextual Info: AVG Semiconductors_DDi Technical Data DV74HC125A Available Q2, 1995 DV74HC125A DV74HCT125A Quad 3-State Noninverting Buffer This device is a noninverting buffer to be used with 3-state memory address drivers, clock drivers, and other bus-oriented

Contextual Info: AVG DDi Semiconductors Technical Data DV74HCT640 Available Q2, 1995 DV74HC640A DV74HCT640 Octal 3-State Inverting Bus Transceiver This device is a 3-State transceiver to be utilized in 2-way communication between data buses. The I/O ports are taken into high-impedance states using an active-low

Contextual Info: AVG DDi Semiconductors Technical Data D V 74H C T175 A vailable Q2, 1995 DV74HC175 DV74HCT175 Quad D Flip-Flop with Common Clock and Reset This device consists of four D flip-flops with the common Reset and Clock inputs, and seperate D inputs. Reset active-low

Contextual Info: AVG Semiconductors DDi Technical Data DV74HC00A DV74HCT00A Quad 2-Input NAND Gate This device contains four independent gates, each of which performs the logic NAND function. • • • • • N Suffix Plastic DIP AVG-001 Case Output Drive Capability: 10 LSTTL Loads

ANIC

Abstract: LS112 S125 DC74HC112
Contextual Info: AVG Semiconductors _ DPP Technical Data DV74HCT112 Available Q2. 1995 DV74HC112 DV74HCT112 Dual J-K Flip-Flop with Set and Reset This device identical in pinout to the LS 1 12. Each flip-flop is negative-edge clocked and has active-low asynchronous Set

0301L

Contextual Info: AVG DDi“ Sem iconductors T e c h n ic a l D ata DV74HCT175 Available Q 2 . 1995 DV74HC175 DV74HCT175 Quad D Flip-Flop with Common Clock and Reset This device consists of four D flip-flops with the common Reset and Clock inputs, and seperate D inputs. Reset active-low

HC367

Abstract: 367 al HC365
Contextual Info: AVG DDr Semiconductors Technical Data A vailable 0 2 ,1 9 9 5 DV74HC365, DV74HCT365 DV74HC367, DV74HCT367 Hex Tri-State Buffer These devices are High Speed Non-Inverting Buffers. Both devices have active-low enables. All six gates are controlled in the HC365, 2-Bits and 4-Bits are seperately

iran

Abstract: LS245 S125 HC245A 245a TI
Contextual Info: AVG Semiconductors DDT Technical Data DV74HC245A DV74HCT245A Octal 3-State Noninverting Bus Transceiver The DV74HC245A and DV74HCT245A are identical in pinout to the LS245. This 3-state non-inverting transceiver is used for 2-way asynchronous commmunication between data

HC240A

Abstract: HC244A hct 244a DV74HC244-DV74HCT244 DV74HC240A Y32L DV74HC241-DV74HCT241 A42j
Contextual Info: AVG Semiconductors D D i Technical Data Octal 3-State Inverters/ Line Drivers DV74HC240A, 241 A, 244A DV74HCT240A, 241 A, 244A These devices are designed to be used with 3-state memory address driver, and other bus-orientated systems. N Suffix Plastic DIP

HC04

Abstract: LS04 LS14 S125 DV74HC14A
Contextual Info: AVG DDT Semiconductors Technical Data Hex Schmitt-Trigger Inverter DV74HC14A DV74HCT14A The DV74HC14A inverter is identical in pinout to the LS14, LS04, and HC04. The inputs are compatible with standard CMOS outputs. W ith pullup resistors, they are compatible with

HC138A

Abstract: HC-138A S125
Contextual Info: AVG DDi Semiconductors Technical Data DV74HC138A DV74HCT138A 1-of-8 Decoder/Demultiplexer This device decodes a three-bit Address to one-of-eight active-low outputs. This device features three Chip Select In­ puts, tw o active LOW, one active HIGH •

Contextual Info: AVG Semiconductors_DPi Technical Data Available Q2, 1995 DV74HC126A DV74HCT126A Quad 3-State Noninverting Buffer This device is a noninverting buffer to be used with 3-state memory address drivers, clock drivers, and other bus-oriented

74 ls132

Contextual Info: AVG Semiconductors DDi Technical Data DV74HCT132 Available Q 2 ,1995 Quad 2-Input NAND Gate with Schmitt-Trigger Input D V 74 H C 132 A D V 74 H C T 132 A The DV74HC132A is identical in pinout to the LS132. The inputs are compatible with standard CMOS outputs; with pullup

Contextual Info: AVG Semiconductors DDi Technical Data DV74HC373A DV74HCT373A Octal 3-State Non-Inverting Transparent Latch Pinout for the ’HC373A and ’HCT373Aare identical to the LS373. The Output Enable input does not affect the state of the latches, but when the Output Enable is high, all device out­

Contextual Info: AVG Semiconductors DDiT Technical Data DV74HCT139A Available Q2, 1995 Dual 1-oM Decoder/ Demultiplexer DV74HC139A DV74HCT139A This device consists of two ¡dependent 1-of-4 decoders, each of which decodes a 2-bit Address to 1-of-4 active-low outputs. Active-low Selects are provided to facilitate the demultiplexing

850C

Abstract: S125
Contextual Info: AVG Semiconductors DDT Technical Data DV74HC10 DV74HCT10 Triple 3-Input NAND Gate This device contains three independent gates, each of which performs the logic NAND function. N Suffix Plastic DIP AVG-001 Case • Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL

Contextual Info: AVG Semiconductors DDi Technical Data Available Q 2 ,1995 4-Bit Full Adder DV74HC283 DV74HCT283 These devices are high-speed 4-bit binary Full Adders with internal carry look-a-head. The device adds two 4-bit words A and B plus the Carry-ln bit. The binary sum appears at the

Contextual Info: AVG DDi Semiconductors Technical Data DV74HC04A DV74HCT04A Hex Inverter This device contains six independent three-stage inverters, each of which performs the logic INVERT function. • Output Drive Capability: 10 LSTTL Loads • • Outputs Directly Interface to CMOS, NMOS, and TTL

Contextual Info: AVG Semiconductors_ DDr Technical Data DV74HCT253 Available Q2, 1995 Dual 4-Input Data Selector/ Multiplexer with 3-State Outputs DV74HC253 DV74HCT253 The Address inputs select one of four Data inputs from each multiplexer. Each multiplexer has an active-low Output

Contextual Info: AVG Semiconductors DDr Technical Data Available Q2, 1995 DV74HC279 DV74HCT279 Quad Set-Reset Latch This device consists of four independent set-reset input latches. Each latch has its normal output available. Two latches have two seperate sets available. •

Contextual Info: AVG Semiconductors DDi Technical Data Available Q2, 1995 Phase Locked Loop DV74HC4046A This device contains 3-phase comparators, a voltage controlled oscillator, and an op-amp. The comparators have two input signals SIG and COMP that are common to all.

Contextual Info: AVG Semiconductors DDi Technical Data DV74HC138A DV74HCT138A 1-of-8 Decoder/Demultjplexer This device decodes a three-bit Address to one-of-eight active-low outputs. This device features three Chip Select In­ puts, two active LOW, one active HIGH • Output Drive Capability: 10 LSTTL Loads