DSV 11 Search Results

AN901

Abstract: ND2012L ND2020 ND2020L 37807
Contextual Info: ND2012L/2020L Siliconix NĆChannel DepletionĆMode MOS Transistors Product Summary Part Number V BR DSV Min (V) ND2012L rDS(on) Max (W) VGS(off) (V) ID (A) 12 -1.5 to -4 0.16 20 -0.5 to -2.5 0.132 200 ND2020L For applications information see AN901. Features

N-Channel Depletion-Mode MOSFET

Abstract: TA 7061 52426 ND2020L
Contextual Info: Temic ND2012L/2020L Semiconductors N-Channel Depletion-Mode MOSFET Transistors Product Summary P a rt N um ber V<BR DSV M in V) ND2012L ND2020L 200 Features • • • • • High Breakdown Voltage: 220 V Normally “On” Low rDS Switch: 9 Q Low Input and Output Leakage

Contextual Info: Te m ic siiiconix_ ND2012L/2020L N-Channel Depletion-Mode MOS Transistors Product Summary Part Number v BR DSV ND2012L Min (V) r i)S(on) Max (£2) 200 ND2020L Id Vg s (oB) (V) (A) 12 -1.5 to - 4 0.16 20 -0.5 to -2.5 0.132 For applications information see AN901, page 12-46.

Contextual Info: 19-2864; Rev 5; 11/07 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9214/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing

STM TO 247 package inductance

Contextual Info: H ÎYY^s JL flHVw A- Ik»!? HiPerFET Power MOSFETs V DSS IXFH IXFH IXFH IXFH N-Channel Enhancement Mode High dv/dt, L o w trr, HDM O S™ Family 76 76 76 76 N06-11 N06-12 N07-11 N07-12 60 60 70 70 V V V V D DS on ^D25 76 76 76 76 A A A A 11 12 11 12 mQ

Contextual Info: Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPD6F002-Q1 SLLSEK0A – DECEMBER 2014 – REVISED FEBRUARY 2015 TPD6F002-Q1 Automotive ESD Protection and EMI Filter for LCD Displays and FPD-Link 1 Features 3 Description

UTP cat 6 cable

Contextual Info: 19-2828; Rev 5; 3/12 KIT ATION EVALU E L B A IL AVA Programmable DC-Balanced 21-Bit Serializers Features The MAX9209/MAX9213 serialize 21 bits of LVTTL/ LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides

max9234

Abstract: MAX9234EUM MAX9236EUM MAX9238
Contextual Info: 19-3641; Rev 0; 4/05 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers The MAX9234/MAX9236/MAX9238 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel-rate LVDS clock received with the LVDS data streams provides timing for

Contextual Info: 19-2828; Rev 5; 3/12 KIT ATION EVALU E L B A IL AVA Programmable DC-Balanced 21-Bit Serializers Features The MAX9209/MAX9213 serialize 21 bits of LVTTL/ LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides

Contextual Info: 19-3641; Rev 0; 4/05 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers The MAX9234/MAX9236/MAX9238 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel-rate LVDS clock received with the LVDS data streams provides timing for

Contextual Info: MAX9234/MAX9236/ MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers General Description The MAX9234/MAX9236/MAX9238 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel-rate LVDS clock received with the LVDS data streams provides timing for

DS90CR215

Abstract: DS90CR217 MAX9209 MAX9209ETM MAX9209EUM MAX9210 MAX9211 MAX9213ETM
Contextual Info: 19-2828; Rev 2; 2/04 Programmable DC-Balanced 21-Bit Serializers Features The MAX9209/MAX9211/MAX9213/MAX9215 serialize 21 bits of LVTTL/LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization.

DS90CR215

Abstract: DS90CR217 MAX9209 MAX9210 MAX9211 MAX9213 MAX9215 marking aaa MAX9213ETM
Contextual Info: 19-2828; Rev 3; 6/07 Programmable DC-Balanced 21-Bit Serializers Features The MAX9209/MAX9211/MAX9213/MAX9215 serialize 21 bits of LVTTL/LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization.

DS90CR216A

Abstract: DS90CR218A MAX9210ETM MAX9210EUM MAX9212ETM
Contextual Info: 19-2864; Rev 0; 4/03 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216 feature programmable DC balance, which allows isolation between serializer and deserializer using AC-coupling. A deserializer decodes data transmitted by a

RGs 14

Abstract: SFs SOT23
Contextual Info: Preliminary Data BSS 169 SIPMOS Small-Signal Transistor • N channel • Depletion mode • High dynamic resistance Pin 1 Pin 2 G Pin 3 S D Type VDS ID RDS on Package Marking Ordering Code BSS 169 100 V 0.12 A 12 Ω SOT-23 SFs Q67000-S322 Maximum Ratings

Contextual Info: TPD6F002 www.ti.com SLLS876A – AUGUST 2008 – REVISED NOVEMBER 2009 SIX-CHANNEL EMI FILTER FOR LCD DISPLAY/KEYPAD APPLICATION Check for Samples: TPD6F002 FEATURES 1 • • • Six-Channel EMI Filtering for Data Ports Robust ESD Protection Exceeds IEC61000-4-2

TI OMAP keypad

Contextual Info: TPD6F002 www.ti.com SLLS876A – AUGUST 2008 – REVISED NOVEMBER 2009 SIX-CHANNEL EMI FILTER FOR LCD DISPLAY/KEYPAD APPLICATION Check for Samples: TPD6F002 FEATURES 1 • • • Six-Channel EMI Filtering for Data Ports Robust ESD Protection Exceeds IEC61000-4-2

Contextual Info: 19-3954; Rev 1; 10/06 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock

Contextual Info: 19-3954; Rev 2; 6/07 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock

Contextual Info: 19-3954; Rev 2; 6/07 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock

MAX9220EUM

Contextual Info: 19-2864; Rev 4; 3/05 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels.

DIAGRAM OF SPEECH COMPRESSION

Abstract: CT8015 dsvd echo modem echo cancellation dsvd
Contextual Info: t nbH Flier' D S P C R O U P . I NC. 1 « ?.• : CT8015 mover Tpi. 0.5 11/ 9 Ci> '4-0 Fax Go 1 1 / 9 Go 64_o4 TRUESPEECH DSVD Co-Processor T he CT8015 is a TRUESPEECH co-processor performing full duplex compression and de-compression functions for D SV D Digital Simultaneous Voice and Data , Modems while maintaining Microsoft Sound System 2.0 and

ND2020L

Contextual Info: A flg S ä VDDQ SERIES DIE N-Channel Depletion-Mode MOS Transistors VDDQ1CHP* VDDQ2CHP* ND2012L ND2020L ‘ Meets or exceeds specification for all part numbers listed below 0.038 ro.965; Source Pad For additional design information please consult the typical performance curves VDDQ20.

tetra-etch

Abstract: 430-FST 330-FTE 134-AWN 134-AWQ TETRAETCH 326-DSV 136-awp 326-DTV balco
Contextual Info: Wire, Cable and Accessories Vishay Micro-Measurements General Information and Selection Different strain gage installation conditions and test specifications often necessitate the use of different types or sizes of leadwires. For accurate, reliable strain measurements, it is important to use an appropriate type of leadwire