DSP210 Search Results

Contextual Info: ANALOG DEVICES DSP Microcomputer ADSP-21065L SDRAM Controller for Glueless Interface to Low Cost External M em ory @ 66 MHz 64M Words External Address Range 12 Programmable I/O Pins and T w o Timers w ith Event Capture Options Code-Com patible w ith ADSP-2106x Family

Contextual Info: ADSP-2106x SHARC DSP Microcomputer Family ADSP-21062/ADSP-21060 ANALOG DEVICES SUMMARY High Performance Signal Processor for Communica­ tions, Graphics, and Imaging Applications Super Harvard ARchitecture Computer SHARC — Four Independent Buses for Dual Data Fetch,

Contextual Info: ADSP-21060 Industrial SHARC DSP Microcomputer Family ADSP-21060C/ADSP-21060LC ANALOG DEVICES SU M M A R Y High Performance Signal Processor for Com munica­ tions, Graphics, and Im aging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch,

DM024

Contextual Info: ANALOG DEVICES 32/40-Bit IEEE Floating-Point DSP Microprocessor □ ADSP-21020 1.1 Scope. This specification covers the detail requirements for a monolithic CMOS 32/40-bit floating-point DSP microprocessor. 1.2 Part Number. The complete pan number per Table 1 of this specification is as follows:

Contextual Info: ANALOG DEVICES 3 V/5 V, 450 iA 16 -B it, Sigma Delta ADC A D 7715 * FEATURES Charge-Balancing ADC 16 Bits No Missing Codes 0.0015% Nonlinearity Programmable Gain Front End Gains of 1, 2 , 32 and 128 Differential Input Capability Three-W ire Serial Interface

Contextual Info: ANALOG D E V IC E S FEATURES Com plete M onolithic Resolver-to-Digital Converter Increm ental Encoder Em ulation 1024-Line Absolute Serial Data (12-Bit) Differential Inputs 12-Bit Resolution Industrial Tem perature Range 20-Lead PLCC Low Power (50 mW) APPLICATIONS

Contextual Info: 32/40-Bit IEEE Floating-Point DSP Microprocessor ADSP-21020 ANALOG DEVICES FUNCTIONAL BLOCK DIAGRAM FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maxim izes Signal Processing Performance 30 ns, 33.3 MIPS Instruction Rate, Single-Cycle

Contextual Info: ADSP-2106X SHARC DSP Microcomputer Family ANALOG DEVICES ADSP-21061/ADSP-21061L S UM M AR Y High Performance Signal Com puter for Speech, Sound, Graphics and Imaging Applications Super Harvard Architecture Com puter SHARC — Four Independent Buses for Dual Data, Instructions,

Contextual Info: ANALOG ► DEVICES LC2M0S Analog I/O Port neously h eld by T rack /H o ld A an d T rack /H o ld B , and the held voltages are sequentially converted. FEATURES Four-Channel, 8-Bit, 3.6 |as ADC Three DACs with On-Chip Amplifiers: One 11-Bit, 8 fis DAC Two 8-Bit, 4 |x.s DACs

Contextual Info: ANALOG DEVICES INC 42E D • OôlbaQD 0D313S3 1 ■ ANA T-5I-07-0I LC2M0S □ AN ALO G D E V IC E S 20-Bit Data Acquisition System AD79024 FEATURES 20-Blt Slgma-Delta ADC Dynamic Range of 105 dB 150 Hz Input ±0.0015% Integral Nonlinearity (150 Hz Input)

7BL05

Abstract: LRDOS AD7871 AD7872 AD7871AQ zener 2a1
Contextual Info: ANALOG DEVICES FEATURES Complete Monolithic 14-Bit ADC 2s Complement Coding Parallel, Byte and Serial Digital Interface 80 dB SNR at 10 kHz Input Frequency 57 ns Data Access Time Low Power—50 mW typ 83 kSPS Throughput Rate 16-Lead SOIC AD7872 LC2M0S Complete 14-Bit Sampling ADCs

Contextual Info: ADSP-2106X SHARC DSP Microcomputer Family ADSP-21060/ADSP-21060L ANALOG DEVICES SU M M A R Y High Performance Signal Processor for Com munica­ tions, Graphics, and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch,

RY 227 Tf 227 10A

Abstract: SD oid 3C
Contextual Info: ADSP- 2106x SHARCF DSP Microcomputer Family ANALOG DEVICES ÆSP-21061/Æ SP-21061L S UM M AR Y High-Performance Signal Com puter for Speech, Sound, Graphics and Imaging Applications Super Harvard Architecture Com puter SHARC — Four Independent Buses for Dual Data, Instructions,

HD14N

Abstract: SP-2111 sp2111 ac tax the ev 2 way tv splitter circuit diagram
Contextual Info: DSP Microcomputer with Host Interface Port ADSP-2111 ANALOG ► DEVICES FEATURES Com plete DSP Microcom puter 60 ns Instruction Cycle Time from 16.67 M Hz Crystal ADSP-2100 Family Code & Function Com patible 2K Words of On-Chip Program M em ory RAM 1K W ord of On-Chip Data M em ory RAM

2388 84 JRC

Abstract: jrc 2388 yx 8018 tdc1008 ADSP-1080 0620 jrc gsp3f Analog Devices Data-Acquisition Databook 1984 ADSP1080 JRC 2388 84
Contextual Info: DSP PRODUCTS DATABOOK DSP MICROPROCESSORS MICROCODED SUPPORT COMPONENTS FLOATING POINT COMPONENTS FIXED POINT COMPONENTS How to Find Product Data in This Databook T H IS V O LU M E Contains Data Sheets, Selection Guides, Application N otes, and a wealth of background inform ation on com ponents for num ber

TSC21020 256

Abstract: ERC32 solar tree abstract DSP-21020 sparc v7 TSC21020F TSC695 TSC695F erc32 3-chip CREME96
Contextual Info: TSC695F: A SEU immune SPARC 32bit computer for space applications Thierry CORBIERE ATMEL Nantes S.A. BP 70602, La Chantrerie 44306 NANTES cedex 3 France thierry.corbiere@nto.atmel.com Abstract After a three-chip set design, the TSC695F, a new monolithic ERC32 brings to space

lt 7720

Abstract: 2s90
Contextual Info: ANALOG D E V IC E S Low Cost, Complete 12-Bit Resolver-to-Digital Converter AD2S90 FEATURES Com plete M onolithic Resolver-to-Digital Converter Increm ental Encoder Em ulation 1024-Line Absolute Serial Data (12-Bit) Differential Inputs 12-Bit Resolution

g21k

Contextual Info: ANDIS013 June 1994 ADSP-21060/62 SHARC Preliminary Data Sheet For current information contact Analog Devices at 617 461-3881 ADSP-21060/62 SHARC Super Harvard Architecture Computer SUM M ARY • • • • • High-Performance Signal Processor for Speech, Sound, Graphics, and Imaging Applications

Contextual Info: ANALOG DEVICES DSP Microcomputer ¿DSP-2183 FUNCTIONAL BLOCK DIAGRAM FEATURES PERFORMANCE 19 ns Instruction Cycle Time from 26.32 MHz Crystal @ 3.3 Volts 52 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in

dsp2187

Abstract: ADSP-2187L
Contextual Info: ANALOG DEVICES FEATURES PERFORMANCE 19 ns Instruction Cycle Tim e @ 3.3 V olts, 52 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture A llow s Dual Operand Fetches in Every Instruction Cycle M ultifunction Instructions

SR-5st

Abstract: 8051 interfacing programming examples 4800 AGM ad7731 MSI MS-5 7731S
Contextual Info: ANALOG DEVICES Low Noise, high Throughput 24-Bit Sgma- Delta ADC AD7731 FEATURES 24-Bit Sigm a-Delta ADC 16 Bits p-p Resolution at 800 Hz Output Rate Program m able Output Rates up to 6.4 kHz Program m able Gain Front End ±0.0015% N onlinearity Buffered Differential Inputs

pt100 interface to 8051

Abstract: pt100 sensor interface WITH 8051 weigh scale calibration program EVAL-AD7714-3EB ad7714_ AD7714-3 AD7714AR-3 AD7714 reference design MQ 6 SENSOR INTERFACING WITH MICROCONTROLLER pt100 sensor interface WITH ADC
Contextual Info: ► A N A LO G D E V IC E S 3 V/5 V, CMOS, 500 pA Signal Conditioning ADC AD7714* FUNCTIONAL BLOCK DIAGRAM FEATURES Charge Balancing ADC 24 Bits No Missing Codes 0.0015% Nonlinearity Five-Channel Programmable Gain Front End Gains from 1 to 128 Can Be Configured as Three Fully Differential

DSP-210X

Abstract: BY262
Contextual Info: Wfipl m L ftm HEW LETT PACKARD Eight Character 5 mm and 7 mm Intelligent Alphanumeric Displays Technical Data Features • X Stackable HDSP-21XX • XY Stackable (HDSP-250X) • 128 Character ASCII Decoder • Programmable Functions • 16 User Definable

Contextual Info: ANALOG DEVICES □ FEATURES Complete DSP Microcomputer 100 ns Instruction Cycle Tim e from 10 MHz Crystal ADSP-2100 Code- & Function-Compatible ADSP-2101 Pin-Compatible 1K W ords of On-Chip Program M em ory RAM 512 Words of On-Chip Data M em ory RAM Dual Purpose Program M em ory for Both Instruction