DS10 Search Results

Luxeon M

Abstract: 4 step MacAdam ellipse definition LXR7-SW40 4 step MacAdam PHILIPS marking Code 5C LXR7-SW57 MacAdam 5700K LXR7
Contextual Info: LUXEON M Array optimized for both high efficacy and high flux density enabling tight beam control Technical Datasheet DS103 LUXEON M High Flux Density and Efficacy Introduction LUXEON M emitters are illumination grade LEDs designed to enable outdoor and industrial applications

DS100BR210

Abstract: 10G-KR
Contextual Info: DS100BR210 Ultra Low Power 10.3 Gbps 2-Channel Repeater with Input Equalization and Output De-Emphasis General Description Features The DS100BR210 is an extremely low power, high performance dual-channel repeater for serial links with data rates up to 10.3 Gbps. The DS100BR210 is configured as two unidirectional channels.

4032V

Abstract: DS1017 LC4032V-10TN48I 4512c application LC4256V-75TN176C marking 17Z 4000B AEC-Q100 DS1020 22z2
Contextual Info: ispMACH 4000V/B/C/Z Family 3.3V/2.5V/1.8V In-System Programmable SuperFAST TM High Density PLDs Coolest Power May 2009 C Features Data Sheet DS1020 TM • Broad Device Offering • Multiple temperature range support – Commercial: 0 to 90°C junction Tj

E3S-DS10C1

Abstract: E3S-DS10B2 10X10 12-240VDC E3S-DS10B1
Contextual Info: E3SE3S-（光头朝前） 系列 外观图 外型尺寸 按检测方式分类 直流 NPN 输出 型 直流 PNP 输出 交流二线 SCR 输出 直接反射型 继 器 触 点 输 出 型 使用直流电源 10-30VDC 输出接 线图 E3S-R2C1 E3S-3C1 图1 常 E3S-DS10C2

MSC23436C

Contextual Info: This version: Apr. 7. 1999 Semiconductor MSC23436C-xxBS10/DS10 4,194,304-word x 36-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE DESCRIPTION The MSC23436C-xxBS10/DS10 is a 4,194,304-word x 36-bit CMOS dynamic random access memory module which is composed of eight 16Mb 4Mx4 DRAMs in SOJ packages and two 8Mb(4Mx2) DRAMs in SOJ packages

54AC05

Abstract: AC05 E20A J14A W14B
Contextual Info: 54AC05 Hex Inverter with Open Drain Outputs General Description Features The ’AC05 contains six inverters. n Outputs sink 24 mA n Open drain for wired NOR function n Standard Microcircuit Drawing SMD 5962-9059001 Logic Symbol IEEE/IEC DS100981-1 Connection Diagrams

DS1666

Abstract: DS2011D 74F04 DS1003 DS1003-16 DS1003-20 DS1003-25 DS1003-33 DS1003-40 DS1003M
Contextual Info: DS1003 DS1003 DALLAS SEMICONDUCTOR FEATURES 4-Tap Silicon Delay Line for RISC A pplications PIN ASSIGNMENT • All-silicon tim e delay IN • Four delayed clock phases from input NC • Input frequency independent NC NC • Precise tap-to-tap delays • Leading and trailing edge precision

Contextual Info: O K I Sem iconductor M S C 2 3 1 4 0 C -X X B S 1 0 /D S 1 0 1,048,576-W o rd x 4 0 -B it D R A M M O D U LE : FAST PAGE M O D E TYP E DESCRIPTION The O K I MSC23140C-xxBS10/DS10 is a fu lly decoded 1,048,576-w ord x 40-bit C M O S Dynam ic Random Access M em ory M odule composed of ten 4-Mb D R A M s 1M x 4 in SO J packages

74F04

Abstract: DS1021 DS1021-25 DS1021-50 DS1021S
Contextual Info: DS1021 nAI I A S DS1021 s e m ic o n d u c t o r Programmable 8-Bit Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay C C C 1 16 2 15 H H 3 14 1 s pi c 4 13 P2 C C C C 5 12 6 11 7 10 8 9 IN • Models with 0.25 ns and 0.5 ns steps E Q/PO

74F04

Abstract: DS1020 DS1020-100 DS1020-15 DS1020-200 DS1020-25 DS1020-50 DS1020S
Contextual Info: DS1020 DALLAS s e m ic o n d u c t o r DS1020 Programmable 8-Bit Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon tim e delay IN • Models with 0.15 ns, 0.25 ns, 0.5 ns, 1 ns, and 2 ns steps 16 ] VCC 2 15 ] OUT Q/PO 3 14 ] P1 4 13 P2 5 12 E • Program m able using 3-wire serial port or 8-bit parallel

Contextual Info: Ferrite Inductors フェライトインダクタ DS106C2 Recommended patterns Inductance Range: 1.2~330H 3.6 推奨パターン図 5.4 10.7 Unit: mm FEATURES •     (Unit: mm) 特長 10.4mm Max. square and 6.8mm Max. height. Magnetically shielded construction and low DC resistance.

Contextual Info: D S 10C P 152Q DS10CP152Q Automotive 1.5 Gbps 2X2 LVDS Crosspoint Switch Texa s In s t r u m e n t s Literature Number: SNLS295D a l DS10CP152Q Sem iconductor Automotive 1.5 Gbps 2X2 LVDS Crosspoint Switch General Description Features The DS10CP152Q is a 1.5 Gbps 2x2 LVDS crosspoint switch

RAS 0510

Abstract: machine maintenance checklist
Contextual Info: O K I Semiconductor MSC23440A-XXBS10/DS10 4,194,304-Word x 40-Bit DRAM MODULE : FAST PAGE MODE TYPE DESCRIPTION The OKI MSC23440A-xxBS10/DS10 is a fully decoded 4,194,304-word x 40-bit CMOS Dynamic Random Access Memory Module composed of ten 16-Mb DRAMs 4M x 4 in SOJ packages

MSC23436D

Contextual Info: This version: Mar. 8.1999 O K I Semiconductor MSC23436D-xxBS10/DS10 4,194,304-word x 36-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE DESCRIPTION The MSC23436D-xxBS10/DS10 is a fully decoded, 4,194,304-word x 36-bit CMOS dynamic random access memory module composed of eight 16Mb DRAMs 4Mx4 in SOJ packages and two 8Mb DRAMs (4Mx2) in SOJ

B952AS-1R1N

Abstract: B952AS-1R8N B952AS-2R7N DS104C2
Contextual Info: づ け Fixed Inductors for Surface Mounting 面実装用固定インダクタ DS104C2 Inductance Range: 1.1~120 H Recommended patterns DIMENSIONS／外形寸法図 3.6 推奨パターン図 5.4 10.7 Unit: mm (Unit: mm) FEATURES／特長 • • • •

8 pin IC 1038

Abstract: DS1091L Dither Circuit Diagram 125NC DS1091LUA-XXXX DS1091LUA-XXX
Contextual Info: 19-5768; Rev 1; 3/11 DS1091L Automotive Temperature Range Spread-Spectrum EconOscillator General Description The DS1091L is a low-cost clock generator that is factory trimmed to output frequencies from 130kHz to 66.6MHz with a nominal accuracy of ±0.25%. The device can also

16-PIN

Abstract: delay line 16PIN DS1023-500 DS1023 DS1023-100 DS1023S-500 300MIL DS1023-050 DS1023S-025
Contextual Info: PROGRAMMABLE DELAY LINE HAS 4x IMPROVEMENT IN INTEGRAL LINEARITY DS1023 8-Bit Silicon Delay Line Supports Serial or Parallel Programming The DS1023 programmable delay line, a DS1020/21 upgrade, allows for processor control of signal timing delays via either a 3-wire serial or 8-bit parallel port. The DS1023 is the first programmable delay line to allow

DS1085L

Abstract: DS1085LZ-12 DS1085LZ-25 DS1085LZ-5 J-STD-020A
Contextual Info: DS1085L 3.3V EconOscillator Frequency Synthesizer www.maxim-ic.com PIN ASSIGNMENT FEATURES § § § § § § § § § § § § User-Programmable Frequency Synthesizer Programmable From 4.1kHz to 66MHz Dual Synchronous Outputs 4.13MHz to 66MHz Reference Oscillator

XC5VLX50T-1FFG665C

Abstract: ff1156 VIRTEX-5 DDR2 controller FFG1156 VIRTEX-5 DDR PHY Virtex-5 Ethernet development Virtex-5 LXT Ethernet DSP48E SRL16 XC5VLX220
Contextual Info: R DS100 v5.0 February 6, 2009 Virtex-5 Family Overview Product Specification General Description The Virtex -5 family provides the newest most powerful features in the FPGA market. Using the second generation ASMBL (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choice

clause 22 phy registers

Abstract: 13007 h3 ali 3602 detail of D 13007 K mca exam date sheet 1000BASE-X DS1005 STS-48
Contextual Info: LatticeSC/M Family flexiPCS Data Sheet DS1005 Version 01.9, December 2008 LatticeSC/M Family flexiPCS Data Sheet Table of Contents December 2008 Introduction to flexiPCS .1-1

Contextual Info: DS1012 DS1012 2-in-1 Sub-Miniature Silicon Delay Line with Logic DALLAS SEMICONDUCTOR FEATURES PIN ASSIGNMENT • All-silicon tim e delay • 5 3 |iW m ax. C M O S quiescent m ode 8 H vcc 7 n 6 • Surface mount 8-pin m ini-SO IC and standard 8-pin D IP 5

Contextual Info: DS1012 DS1012 2-in-1 Sub-Miniature Silicon Delay Line with Logic DALLAS SEMICONDUCTOR FEATURES PIN ASSIGNMENT • All-silicon time delay • 53 jiW max. CMOS quiescent mode • Surface mount 8-pin mini-SOIC and standard 8-pin DIP 1N1 £ 1 O UT3C 2 OUT1 Q 3

Contextual Info: DS1007 DS1007 DALLAS SEMICONDUCTOR 7-in-1 Silicon Delay Line PIN ASSIGNMENT FEATURES • All-silicon time delay • 7 independent buffered delays • Delay tolerance ± 2 ns IN 4 OUT4 • Four delays can be custom set between 3 ns and 10 ns GND OUT7 • Three delays can be custom set between 9 ns and

Contextual Info: D S 1000 DALLAS DS1000 5-Tap Silicon Delay Line SEMICONDUCTOR PIN ASSIGNMENT FEATURES • All-silicon time delay IN [ 1 T 7 14 D Vce IN £ 1 NC NCC 2 • 5 taps equally spaced NC[ 2 13 ] • Delays are stable and precise n c[ 12 ] TAP 1 3 TAP 2 £ 4 • Both leading and trailing edge accuracy