DQ571 Search Results

Thyristor mw 134

Abstract: TRIAC BR100
Contextual Info: N AMER PHILIPS/DISCRETE b'îE ]> •! bbS3T31 DQ571S4 P h jjjp s S e m ic o n d u c t ^ _ Silicon bi-directionai trigger device D E S C R IP T IO N 3DH * A P X P re lim in a ry s p e c ific a tio n BR100/05 Q U IC K R E F E R E N C E DATA Silicon bi-directional trigger device

J32CG

Abstract: 61a3 mosfet BCM5461KFB 61a3 58A6 bcm5461 60F10 L32SD DQ27152 A26B4
Contextual Info: 1 2 4 3 5 6 7 TABLE OF CONTENTS F F PAGE 02 - BLOCK DIAGRAM PAGE 03 - 750GX ADDRESS/DATA BUSSES PAGE 04 - 750GX CONTROLS AND GROUND PAGE 05 - 750GX POWER AND DECOUPLING PAGE 06 - TSI108 PROCESSOR BUS INTERFACE PAGE 07 - TSI108 MEMORY INTERFACE PAGE 08 - DDR2 DIMM CONNECTOR SLOT 0

DQ2060

Abstract: DC1065 EB285 EBSA-285 R164 SA110 B20B20 A59A59 CPU-A13 CPUD22
Contextual Info: A B C D COPYRIGHT C 8 1997 DIGITAL EQUIPMENT CORPORATION 8 16 17 18 19 20 21 sht sht sht sht sht sht 7 CHK CHANGE NO. REV CPU, CPU_, a Block Address X-Bus XBUF_, have PCI +3V Stand - +2V, - - - TAG_,RST_ - - 6 bidirects this 5 is Debug Port their Serial Spare

PBSRAM

Abstract: 80364K64 DQ571
Contextual Info: MC 8 0 3 6 4K 64 Low M o S ys Power 3.3V/2.5V 64K x 64 P B S R A M High perform ance, low pow er pipeline burst SRAM • Ultra low pow er single chip 512Kbyte Cache for green PC and battery pow ered PC 2 High perform ance • • • • 83-133M Hz Speed grades

Contextual Info: DATA SHEET NEC / MOS INTEGRATED CIRCUIT _ / ¿ / P D 4 2 S 4 2 1 A , 4 2 4 2 1 A 4 M-BIT DYNAMIC RAM 256 K-WORD BY 16-BIT, HYPER PAGE MODE, BYTE READ/WRITE MODE Description The /JPD42S4210A, 424210A are 262 144 words by 16 bits dynamic CMOS RAMs with optional hyper page

Contextual Info: PH I L I P S INTERNATIONAL Data sheet status Product specification date of issue July 1990 bOE T> • 711üôab 00S710M S && IPHIN LTD351 Liquid Crystal Display QUICK REFERENCE DATA DEVICE DESCRIPTION The LTD351 is a bargraph display. Typical applications

Contextual Info: IBM11N32645B IBM11N32735B IBM11N32645C IBM11N32735C 32M x 64/72 DRAM Module Features • 168-Pin JEDEC-Standard Unbuffered 8-Byte Dual In-Line Memory Module • 32Mx64, 32Mx72 Dual Bank Extended Data Out Page Mode DIMMs • Performance: • System Performance Benefits:

Contextual Info: HB56UW1673EN-6A/7A Preliminary 16,777,216-Word x 72-Bit High Density Dynamic RAM Module 168-pin JEDEC Standard Outline Unbuffered 8BYTE DIMM HITACHI The HB56UW 1673EN belongs to 8 Byte DIMM Dual In-line Memory Module family, and has been developed as an optimized main memory solution

CPU-A13

Abstract: EB285 EBSA-285 SA110 ad15 B17B17 A54A CPUD22 DQ511 DC1065
Contextual Info: 8 7 6 5 EBSA-285 SHEET SIG 4 Schematic PREFIXES 3 2 1 BAN#=EB285 21285 REV#=REVAX04 Directory EVALUATION BOARD DESCRIPTION D D C sht 1 - Schematic sht 2 - Block sht 3 CPU_, sht 4 XBUS_ Debug pick-up sht 5 FBG_,PCI_ 21285 ’Footbridge’ sht 6 BUF_ sht 7