DM74LS1 Search Results

DM54LS174

Abstract: 54LS174 54LS174DMQB 54LS174FMQB 54LS175 DM54LS175 DM74LS174 DM74LS175 LS174 LS175
Contextual Info: 54LS174 DM54LS174 DM74LS174 54LS175 DM54LS175 DM74LS175 Hex Quad D Flip-Flops with Clear General Description Features These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic All have a direct clear input and the quad 175 versions feature complementary

74LS11

Abstract: MK2870-10N05 DM74LS11 DM74LS11M DM74LS11N M14A MS-001 N14A
Contextual Info: Revised March 2000 DM74LS11 Triple 3-Input AND Gate General Description This device contains three independent gates each of which performs the logic AND function. Ordering Code: Order Number Package Number Package Description DM74LS11M M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, 0.150 Narrow

74LS151

Abstract: DM74LS151 DM74LS151M DM74LS151N DM74LS151SJ M16A M16D MS-001 N16E
Contextual Info: Revised March 2000 DM74LS151 1-of-8 Line Data Selector/Multiplexer General Description Features This data selector/multiplexer contains full on-chip decoding to select the desired data source. The DM74LS151 selects one-of-eight data sources. The DM74LS151 has a

dm74ls174n

Contextual Info: Revised April 2000 DM74LS174 • DM74LS175 Hex/Quad D-Type Flip-Flops with Clear General Description Features These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the quad 175 versions feature complementary

multiplexer

Abstract: multiplexer 2to1 selector transistors bipolar DM74150 DM74157 DM74ALS151 DM74ALS153 multiplexer/14052B DM74AS157
Contextual Info: Logic Products by Function Selector Products Logic Product Family Product Description Package Voltage Node DM74150 Bipolar-TTL Data Selector/Multiplexer DIP 5 DM74ALS151 Bipolar-ALS 1 of 8 Line Data Selector/Multiplexer DIP SOIC 5 DM74LS151 Bipolar-LS 1-of-8 Line Data Selector/Multiplexer

Contextual Info: S E M IC O N D U C T O R tm DM74LS138, DM74LS139 Decoders/Demultiplexers General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applica­ tions, requiring very short propagation delay times. In

Contextual Info: S E M IC O N D U C T O R tm DM74LS136 Quad 2-Input Exclusive-OR Gate with Open-Collector Outputs General Description This device contains four independent gates, each of which perform s the logic exclusive-O R function. Connection Diagram Dual-ln-Line Package

74LS112AN

Abstract: 74LS112AM
Contextual Info: I R C H I L D S E M I C O N D U C T O R TM DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains tw o independent negative-edge-triggered J-K flip-flops w ith com plem entary

DM74LS126AN

Contextual Info: S E M IC O N D U C T O R tm DM74LS126A Quad 3-STATE Buffer Buffer Connection Diagram Dual-ln-Line Package V cc C4 A4 Y4 C3 A3 Y3 DSOO6388-1 Order Number DM74LS126AM or DM74LS126AN See Package Number M14A or N14A Function Table Y = A Inputs Output A C L H L

dm74ls16

Contextual Info: S E M IC O N D U C T O R tm DM74LS169A Synchronous 4-Bit Up/Down Binary Counter th e c a rry o u tp u ts . T h e c a rry o u tp u t th u s e n a b le d w ill p ro d u c e T h is s y n c h ro n o u s p re s e tta b le c o u n te r fe a tu re s an in te rn a l

multiplexers 74 LS 150

Contextual Info: S E M IC O N D U C T O R tm DM74LS157/DM74LS158 Quad 2-Line to 1-Line Data Selectors/Multiplexers General Description • S o u rc e p ro g ra m m a b le c o u n te rs T h e s e d a ta s e le c to rs /m u ltip le x e rs c o n ta in in v e rte rs a n d d riv ­

74LS165N

Abstract: 54LS165J
Contextual Info: EM ICONDUCTQ R t DM74LS165 8-Bit Parallel In/Serial Output Shift Registers General Description This device is an 8-bit serial sh ift register w hich shifts data in the direction of Q A tow ard Q H w hen clocked. Parallel-in ac­ cess is m ade available by eight individual direct d ata inputs,

DM 0356

Abstract: ic dM 0365 R dm 0365 r
Contextual Info: S E M IC O N D U C T O R tm DM74LS132 Quad 2-Input NAND Gates with Schmitt Trigger Inputs General Descriotion w hich increases th e noise im m unity and transform s a slow ly changing input signal to a fa s t changing, jitte r free output. This device contains fo u r independent gates each of which

54LS138FMQB

Abstract: DM74LS138N DM74LS138 LS139 DM74LS138 Application 54LS138 54LS138DMQB 54LS138LMQB 54LS139 DM74LS139
Contextual Info: DM74LS138, DM74LS139 Decoders/Demultiplexers General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be

DM74LS195AN

Abstract: DM74LS195A 54LS195A 54LS195ADMQB 54LS195AFMQB 54LS195ALMQB DM74LS195AM E20A J16A M16A
Contextual Info: 54LS195A DM74LS195A 4-Bit Parallel Access Shift Register General Description Features This 4-bit register features parallel inputs parallel outputs J-K serial inputs shift load control input and a direct overriding clear All inputs are buffered to lower the input drive

9821

Abstract: MAX PLUS II free alu DM74LS181N CIRCUIT DIAGRAM CNA4 C1995 DM54LS181 DM54LS181J DM54LS181W DM74LS181 DM74LS181N
Contextual Info: DM54LS181 DM74LS181 4-Bit Arithmetic Logic Unit General Description Features The ’LS181 is a 4-bit Arithmetic Logic Unit ALU which can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations Y Y Y Provides 16 arithmetic operations add subtract compare double plus twelve other arithmetic operations

BCD 8421

Abstract: binary to BCD 8421 BCD 8421 application LS162 MC1455P1S synchronous counter using 4 flip flip 54LS160A 54LS160ADMQB 54LS160AFMQB 54LS160ALMQB
Contextual Info: 54LS160A DM74LS160A 54LS162A DM74LS162A Synchronous Presettable BCD Decade Counters General Description Features The ’LS160 and ’LS162 are high speed synchronous decade counters operating in the BCD 8421 sequence They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus

16-LINE

Abstract: 4-line to 16-line decoder DM74LS154 DM74LS154N DM74LS154WM M24B MS-011 MS-013 N24A
Contextual Info: Revised July 2003 DM74LS154 4-Line to 16-Line Decoder/Demultiplexer General Description Features Each of these 4-line-to-16-line decoders utilizes TTL circuitry to decode four binary-coded inputs into one of sixteen mutually exclusive outputs when both the strobe

DM74LS195AN

Abstract: DM54LS195AJ DM74LS195AM J16A M16A N16A
Contextual Info: DM54LS195A/DM74LS195A National Semiconductor Corporation DM54LS195A/DM74LS195A 4-Bit Parallel Access Shift Register General Description Features This 4-bit register features parallel inputs, parallel outputs, J-K serial inputs, shift/load control input, and a direct over­

dm74 Series

Abstract: 63821 54LS112 54LS112DMQB 54LS112FMQB DM54LS112AJ DM54LS112AW DM74 DM74LS112AN LS112AM
Contextual Info: LS112A National Semiconductor 54LS112/DM54LS112A/DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and

54LS181DMQB

Abstract: 54LS181 54LS181FMQB DM74LS181N J24A N24A W24C MAX PLUS II free alu
Contextual Info: National Semiconductor 54LS181/DM74LS181 4-Bit Arithmetic Logic Unit General Description Features The ’LS181 is a 4-bit Arithmetic Logic Unit ALU which can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations.

BCD 8421

Abstract: binary to BCD 8421 DM74 DM74LS196 DM74LS196M DM74LS196N LS196 M14A N14A
Contextual Info: LS196 National Semiconductor DM74LS196 Presettable Decade Counter General Description Features The ’LS196 decade ripple counter is partitioned into divideby-two and divide-by-five sections which can be combined to count either in BCD 8421 sequence or in a bi-quinary

DM74LS154N

Contextual Info: DM54LS154,DM74LS154 DM54LS154 DM74LS154 4-Line to 16-Line Decoders/Demultiplexers Literature Number: SNOS284A DM54LS154 DM74LS154 4-Line to 16-Line Decoders Demultiplexers General Description Features Each of these 4-line-to-16-line decoders utilizes TTL circuitry to decode four binary-coded inputs into one of sixteen

54LS155DMQB

Abstract: 54LS155FMQB 54LS155LMQB 54LS156DMQB DM54LS155J DM54LS155W DM74LS155M DM74LS155N LS155 LS156
Contextual Info: S E M IC O N D U C T O R tm DM74LS155/DM74LS156 Dual 2-Line to 4-Line Decoders/Demultiplexers General Description Features These TTL circuits feature dual 1 -line-to-4-line d em ultiplex­ ers with individual strobes and com m on binary-address in­ puts in a single 16-pin package. W hen both sections are e n ­