DM54S Search Results

TLO6

Abstract: 74S242 74S243 S243 74S242N
Contextual Info: DM 54S242/ DM 74S242. DM54S243/DM74S243 Quadruple Bus Transceivers General Description Absolute Maximum Ratings Note d These four data line transceivers are designed for asyn­ chronous two-way communications between data buses. They can be used to drive terminated lines down to 133

DM74S22

Contextual Info: DM54S22/DM74S22 National Semiconductor DM54S22/DM74S22 Dual 4-Input NAND Gates with Open-Collector Outputs General Description Absolute Maximum Ratings Note 1 T h is d e v ic e c o n ta in s fo u r in d e p e n d e n t g a te s e a ch o f w h ic h p e rfo rm s th e lo g ic N A N D fu n c tio n . T h e ope n c o lle c to r o u tp u ts re q u ire e x te rn a l p u ll-u p re s is to rs fo r

Contextual Info: S240 • S241 • S244 National Sem iconductor DM54S240/DM74S240, DM54S241/DM74S241, DM54S244/DM74S244 Octal TRI-STATE Buffers/Line Drivers/Line Receivers General Description These buffers/line drivers are designed to improve both the performance and PC board density of TRI-STATE buffers/

Contextual Info: S194 National Semiconductor DM54S194/DM74S194 4-Bit Bidirectional Universal Shift Registers Shift right is accomplished synchronously with the rising edge of the clock pulse when SO is high and S1 is low. Serial data for this mode is entered at the shift-right data

AL S86

Contextual Info: ^N atio n al æ æ Semiconductor DM54S86/DM74S86 Quad 2-Input Exclusive-OR Gates General Description This device contains four independent gates each of which performs the logic Exclusive-OR function. Connection Diagram Dual-ln-Line Package Vcc ! 14 A1 84

Contextual Info: National Æii Semiconductor DM54S20/DM74S20 Dual 4-Input NAND Gates General Description This device contains two independent gates each of which performs the logic NAND function. Connection Diagram Dual-ln-Une Package C2 NC B2 Tl/F/6449-1 Order Number DM54S20J, DM54S20W or DM74S20N

Contextual Info: S E M I C O N D U C T O R tm DM74S133 13-Input NAND Gate General Description This device contains a single gate which performs the logic NAND function. Connection Diagram Dual-ln-Line Package Vcc M L K J I H Y DS006462-1 Order Number DM54S133J, DM74S133M or DM74S133N

Contextual Info: DM54S22/DM74S22 2 National Sem iconductor DM54S22/DM74S22 Dual 4-Input NAND Gates with Open-Collector Outputs General Description Absolute Maximum Ratings Note 1 This device con tains fo u r independent gates each o f w hich perform s the logic NAND fun ction. The openc o lle c to r ou tputs require external pull-up resistors for

DM54139W

Abstract: DM54S138J DM54S138W DM54S139J DM74S138N S139
Contextual Info: S138 • S139 ZWANational ÆütSemiconductor DM54S138/DM74S138, DM54S139/DM74S139 Decoders/Demultiplexers General Description Features These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing appli­ cations, requiring very short propagation delay times. In

74S374

Abstract: 74S373 DM54S374J DM54S373J DM74S373N DM74S373WM J20A
Contextual Info: S373 • S374 National Semiconductor DM54S373/DM74S373, DM54S374/DM74S374 TRI-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops General Description These 8-bit registers feature totem-pole TRI-STATE outputs designed specifically for driving highly-capacitive or relative­

C1995

Abstract: DM54S253 DM54S253J DM54S253W DM74S253 DM74S253N J16A N16E S153 W16A
Contextual Info: DM54S253 DM74S253 Dual TRI-STATE 1 of 4 Line Data Selectors Multiplexers General Description Features Each of these Schottky-clamped data selectors multiplexers contains inverters and drivers to supply fully complementary on-chip binary decoding data selection to the

S139

Abstract: DM74S138N DM54139W DM54S138 DM54S138J DM54S138W DM54S139 DM54S139J DM74S138 DM74S139
Contextual Info: DM54S138 DM74S138 DM54S139 DM74S139 Decoders Demultiplexers General Description Features These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times In

C1995

Abstract: DM54S112 DM54S112J DM74S112 DM74S112N J16A N16E
Contextual Info: DM54S112 DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset Clear and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops on the falling edge of

C1995

Abstract: DM54S153 DM54S153J DM74S153 DM74S153N J16A N16E
Contextual Info: DM54S153 DM74S153 Dual 1 of 4 Line Data Selectors Multiplexers General Description Features Each of these data selectors multiplexers contains inverters and drivers to supply fully complementary on-chip binary decoding data selection to the AND-OR-invert gates

DM54139W

Abstract: DM54S138J DM54S138W DM54S139J DM74S138N S139
Contextual Info: June 1989 DM54S138/DM74S138, DM54S139/DM74S139 Decoders/Demultiplexers General Description Features These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing appli­ cations, requiring very short propagation delay times. In

15010

Abstract: DM54S174J DM54S175J DM54S175W DM74S174N DM74S175N J16A S174 DM54S175J/883
Contextual Info: & June 1989 DM54S174/DM74S174, DM54S175/DM74S175 Hex/Quad D Flip-Flops with Clear General Description Features These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the quad 175 versions feature complementary

DM54S151

Abstract: DM54S151W DM74S151N J16A N16E S151 W16A
Contextual Info: June 1989 DM54S151/DM74S151 1-of-8 Data Selector/Multiplexer with Complementary Outputs General Description Features These data selectors/multiplexers contain full on-chip de­ coding to select the desired data source. The ’S151 selects one-of-eight data sources. The ’S151 has a strobe input

36b3

Abstract: DM54S10J DM54S10W DM74S10N J14A N14A W14B
Contextual Info: , Ju n e 1989 DM54S10/DM74S10 Triple 3-Input NAND Gates General Description T h is device co ntain s three independent gates e a c h of w hich perform s the lo gic N A N D function. Connection Diagram Dual-In-Line Package V cc ci VI C3 B3 A3 Y3 A1 B1 A2 B2

DM54S257J

Abstract: DM54S257W DM54S258J DM74S257N DM74S258N J16A
Contextual Info: June 1989 DM54S257/DM74S257, DM54S258/DM74S258 TRI-STATE Quad 1 of 2 Data Selectors/Multiplexers General Description Features These Schottky-clamped high-performance multiplexers feature TRI-STATE outputs that can interface directly with data lines of bus-organized systems. With all but one of the

DM74S04N

Abstract: DM54S04J DM54S04W DM74S04 DM74S04M J14A M14A N14A W14B
Contextual Info: E M IC D N D U C T O R t DM74S04 Hex Inverting Gates General Description This device contains six independent gates each o f which perform s the logic IN VER T function. Connection Diagram Dual-ln-Line Package Order Number DM54S04J, DM54S04W, DM74S04M or DM74S04N

1351d

Abstract: w16b DM54S40J DM54S40W DM74S40N J14A N14A
Contextual Info: June 1989 DM54S40/DM74S40 Dual 4-Input NAND Buffers General Description This device contains two independent gates each of which performs the logic NAND function. Connection Diagram Dual-In-Line Package V ç . l „ 02 C2 NC 12 13 B2 A2 10 |l1 Y2 9 3 1 A1

DM54S30

Abstract: DM54S30J DM54S30W DM74S30N J14A N14A W14B
Contextual Info: June 1989 DM54S30/DM74S30 8-Input NAND Gate General Description This device contains a single gate which performs the logic NAND function. Connection Diagram Dual-In-Line Package Vcc I 14 NC H I 13 G NC 11 12 IMC 1 10 Y 19 8 — I 1 A 3 2 4 5 6 B C E F I7

preset 100 K

Abstract: DM54S112 DM54S112J DM74S112 DM74S112N J16A N16E
Contextual Info: , June 1989 DM54S112/DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig­ gered J-K flip-flops with complementary outputs. The J and

DM54S133J

Abstract: DM74S133 DM74S133M DM74S133N J16A M16A N16E
Contextual Info: S E M IC O N D U C T O R tm DM74S133 13-Input NAND Gate General Description This device contains a single gate which perform s th e logic NAND function. Connection Diagram Dual-ln-Line Package Vcc M L K J I H Y DS006462-1 Order Number DM54S133J, DM74S133M or DM74S133N