DIN31 Search Results

6206a

Abstract: K-Line transceiver w1p 84 st10f2xx sigma asc 333 24 pin K-line ST10F276E W1P 59 st10 Bootstrap st10273e
Contextual Info: ST10F276E 16-bit MCU with MAC unit 832 Kbyte Flash memory and 68 Kbyte RAM Datasheet − production data Features • ■ ■ ■ ■ ■ Highly performance 16-bit CPU with DSP functions – 31.25ns instruction cycle time at 64MHz max CPU clock – Multiply/accumulate unit MAC 16 x 16-bit

SM7060

Abstract: 140MHz IF demodulator IC SD7060 SD706 AN993 ISL83700EVAL ISL83740EVAL ISL87060 ISL87060DIK DIN616
Contextual Info: Intersil's ISL83700EVAL and ISL83740EVAL Evaluation Kits provide a means to efficiently evaluate the performance of the ISL837030/ISL83740 Modem Reference Designs and ISL87060 Modem Chip Set. This kit includes everything needed to exercise and monitor the performance of the modem in a laboratory environment.

Contextual Info: > 4M C C DEVICE SPECIFICATION 33 x 32 1.25 G B IT/S D IFF E R E N T IA L CR O SSPO IN T SW ITCH S2028 GENERAL DESCRIPTION FEATURES 33 x 32 differential crosspoint switch Full broadcast switching capability Differential 10K PECL data path Configurable differential output driver

D3318

Abstract: direct pm modulation circuit PDSP16350 PDSP16488A PDSP16510A COS10
Contextual Info: PDSP16350 PDSP16350 I/Q Splitter/NCO Supersedes version in December 1993 Digital Video & DSP IC Handbook, HB3923-1 The PDSP16350 provides an integrated solution to the need for very accurate, digitised, sine and cosine waveforms. Both these waveforms are produced simultaneously, with 16

Contextual Info: The ARM Processor Family This Data Sheet is one of a series describing the ARM Family of products from GEC Plessey Semiconductors. The table below shows the current range of 32-bit RISC M icroprocessors/M icrocontrollers. GPS Name P ackag e Description 32 bit RISC core with 32 bit address range.

COS10

Abstract: PDSP16350 PDSP16488A PDSP16510A DIN24 PDSP16256/A
Contextual Info: PDSP16350 PDSP16350 I/Q Splitter/NCO DS3711 The PDSP16350 provides an integrated solution to the need for very accurate, digitised, sine and cosine waveforms. Both these waveforms are produced simultaneously, with 16 bit amplitude accuracy, and are synthesised using a 34 bit

Crossbow

Abstract: S 187 S2024B-6 register file DIN31
Contextual Info: DEVICE SPECIFICATION “CROSSBOW” 32 X 32 800 MBIT/S CROSSPOINT SWITCH “CROSSBOW” X 32 800 MBIT/S CROSSPOINT SWITCH BiCMOS PECL 32 CLOCK GENERATOR FEATURES GENERAL DESCRIPTION • Full broadcast switching capability • 32 x 32 crosspoint structure, expandable to 64 x

st10f276 jtag

Abstract: w1p 59 ST10F276 st10 Bootstrap EF52 transistor w2P w1p 83 W1P 76 transistor LQFP144 ST10
Contextual Info: ST10F276 16-bit MCU with MAC unit, 832 Kbyte Flash memory and 68 Kbyte RAM Features • ■ ■ ■ ■ ■ Highly performant 16-bit CPU with DSP functions – 31.25ns instruction cycle time at 64MHz max CPU clock – Multiply/accumulate unit MAC 16 x 16-bit

SCSI 100 connector datasheet

Abstract: DIN28 working of 5 pin relay 100 pin scsi 100-pin SCSI female connector n type connector female CB-89200-2 DIN24 relay 5 pin Backup output protect
Contextual Info: DASP-52064 Isolated 32 D/I & 32 D/O Card Features 32 isolated digital inputs for source type 32 interrupt input I/O digital input 32 isolated digital outputs for sink type 2K battery backup RAM for backup nonvolatile data (only for DASP-52064) One programmable timer and interrupt

ADSP-3221

Contextual Info: ANALOG DEVICES High Speed 64-Bit IEEE Floating-Point ALU ADSP-3221 1.1 Scope. This specification covers the detail requirements for a CMOS monolithic 32-bit and 64-bit IEEE Standard 754 format floating-point arithmetic and logic unit ALU . 1.2 Part Number.

K3192

Contextual Info: DEVICE SPECIFICATION > FEATURES 4 M C C GENERAL DESCRIPTION 33 x 32 differential crosspoint switch Full broadcast switching capability Differential 10K PECL data path Configurable differential output driver controls Up to 1.25 Gbit/s NRZ data rate TTL configuration controls

SS2024

Abstract: 3111z
Contextual Info: DEVICE SPECIFICATION CROSSBOW” 32 X 32 800 MBIT/S CROSSPOINT SWITCH GENERAL DESCRIPTION FEATURES • Full broadcast switching capability • 32 x 32 crosspoint structure, expandable to 64 x 64 with no external components • ECL 10K data path and TTL I/O for configuration

Contextual Info: ST10F272M 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM Datasheet − production data Features • ■ ■ 16-bit CPU with DSP functions – 50ns instruction cycle time at 40 MHz max CPU clock – Multiply/accumulate unit MAC 16 x 16-bit multiplication, 40-bit accumulator

ARM610

Contextual Info: ARM610 Data Sheet Mitel Part Number: P610ARM-B/KG/FPNR Notes 1 The original P610ARM/KG/FPNR is obsolete 2) This datasheet includes the performance data previously supplied in supplement MS4397 - Jan 1996 Preface The ARM610 is a general purpose 32-bit microprocessor with 4kByte cache, write buffer and Memory

S202S

Abstract: ES2025
Contextual Info: DEVICE SPECIFICATION 32 x 32 1.5 G B IT/S D IFFE R E N TIA L C R O SSPO IN T SW ITCH FEATURES • • • • • • • • 32 x 32 differential crosspoint switch Full broadcast switching capability Differential 10K PECL data path Configurable differential output driver

ST10F273M-4Q3

Abstract: diode T35 12H ST10F273 TQFP144 DIMENSION LQFP144 PQFP144 ST10 ST10F273E st10 Bootstrap ST10F273 reprogramming
Contextual Info: ST10F273M 16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAM Features • High performance 16-bit CPU with DSP functions – 50ns instruction cycle time at 40 MHz max CPU clock – Multiply/accumulate unit MAC 16 x 16-bit multiplication, 40-bit accumulator

EN61643-11

Abstract: Superior Electric SVR VARISTOR MOV surge protection circuit diagram
Contextual Info: STABILINE Transient Voltage Surge Suppressors DIN3-70 Series - OWNERS MANUAL Thank you for purchasing the DIN3-70 Series STABILINE Transient Voltage Surge Suppressor . another Superior product!! Expect exceptional performance. The unit is built to the highest

Contextual Info: Introduction 1.0 Introduction The SA-110 microprocessor SA-110 is a general purpose 32-bit microprocessor with a 16KB instruction cache, a 16KB writeback data cache, an 8-entry write buffer with 16 bytes per entry, and a memory management unit (MMU) combined in a single chip. The SA-110 is software compatible with the ARM V4 architecture processor family and

max2960

Contextual Info: M3E D APPLIED MICRO CIRCUITS • 000^002 0Ü0Q7SQ T ■ AMCC PRELIMINARY DEVICE SPECIFICATION T - S h ll S2024 “ CROSSBOW” 3 2 X 3 2 1.2 GBIT/S CROSSPOINT SWITCH DESCRIPTION FEATURES • Full broadcast switching capability • 32 x 32 crosspoint structure, expandable to 64 x 64

Contextual Info: ANALOG DEVICES High Speed 64-Bit IEEE Floating-Point Multiplier _ ADSP-3210 1.1 Scope. This specification covers the detail requirements for a CMOS monolithic 32-bit and 64-bit IEEE Standard 754 format floating-point multiplier.

Contextual Info: ANALOG DEVICES High Speed 64-Bit IEEE Floating-Point ALU _ ADSP-3220 1.1 Scope. This specification covers the detail requirements for a CMOS monolithic 32-bit and 64-bit IEEE Standard 754 format floating-point arithmetic and logic unit ALU .

din32

Abstract: CORDIC to generate sine wave PDSP16350 PDSP16488A PDSP16510A D3318
Contextual Info: PDSP16350 PDSP16350 I/Q Splitter/NCO DS3711 The PDSP16350 provides an integrated solution to the need for very accurate, digitised, sine and cosine waveforms. Both these waveforms are produced simultaneously, with 16 bit amplitude accuracy, and are synthesised using a 34 bit

TJA 1145

Abstract: S2028A
Contextual Info: DEVICE SPECIFICATION 33 x 32 1.25 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH 33 x 32 1.25 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH GENERAL DESCRIPTION FEATURES • • • • • • • • • • • 33 x 32 differential crosspoint switch Full broadcast switching capability

oasis

Abstract: S2025 DIN20P
Contextual Info: DEVICE SPECIFICATION 32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH 32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH FEATURES • • • • • • • • GENERAL DESCRIPTION 32 x 32 differential crosspoint switch Full broadcast switching capability