DELAY111 Search Results

84C300A

Contextual Info: Full Duplex 84C 300A 4-Port Fast Ethernet Controller Technology Incorporated PRELIMINARY _April 19, 1996 Features • Low Power CMOS Technology ■ 4-Port Ethernet Controller Optimized for Note: Check for latest Data Sheet revision

Contextual Info: « LOW-POWER HEX PECL-TO-TTL TRANSLATOR SYNERGY SEMICONDUCTOR FE A T U R E S PRELIMINARY SY100S390 DESCRIPTION The SY100S390 is a hex PECL-to-TTL translator for converting 100K logic levels to TTL logic levels. Unlike other level translators, the SY100S390 operates using only one

84C30A

Abstract: 051b3
Contextual Info: Full Duplex S4C30A 4-Port Technology Incorporated Ethernet Controller PRELIMINARY April 19, 1996 Features • ■ Note: Check for latest Data Sheet revision before starting any designs. Low Power CMOS Technology ■ Meets A NSI/IEEE802.3 and ISO 8802-3 Standards

SY-510

Abstract: 7006L 7006S
Contextual Info: OlDT HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM Features * * * * IDT7006S/L one d evice_ M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling

palc22v10d programming guide

Contextual Info: Flash Erasable, Reprogrammable CMOS PAL Device Features • Advanced second-generation PAL architecture • Low power — 90 mA max. commercial 10 ns — 130 mA max. commercial (7.5 ns) • CMOS Flash EPROM technology for electrical erasabllity and reprogrammablllty

s3102

Abstract: MS310256-15PC
Contextual Info: MOSEL MS310256 32,768x8 CMOS Mask Programmable ROM FEATURES DESCRIPTION • Access time: 150ns max The MS310256 is a high performance Read Only Memory organized as 32,768 words by 8 bits. It is designed to be compatible with all microprocessors and similar applications where high performance

pll 566

Abstract: pll 565 application pll 565 DJZ capacitor CA1310 565 PLL AD P71 CA10 CA12 elan microelectronics 1999
Contextual Info: ICE567 User manual FOR EM78565 EM78566 EM78567 Version 1.0 ELAN MICROELECTRONICS CORP. No. 12, Innovation 1st RD., Science-Based Industrial Park Hsin Chu City, Taiwan, R.O.C. TEL: 03 5639977 FAX: (03) 5630118 EM78567/566/565 Manual EM78P567/566/565 Manual

Contextual Info: 11S8>s\i jdt HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM IDT7007S/L Integrated Device Technology, Inc. FEATURES: • True Dual-Ported memory cells which allow simulta­ neous reads of the same memory location • High-speed access — Military: 25/35/55ns max.)

Contextual Info: HIGH SPEED 3.3V 2K X 8 DUAL-PORT STATIC RAM WITH INTERRUPTS IDT71V321S/L IDT71V421S/L Features * * High-speed access ♦ BUSY output flag on IDT71V321; BUSY input on IDT71V421 - Industrial: 25ns max. * Fully asynchronous operation from either port - Commercial: 25135155ns (max.)

SY 3803 12A

Abstract: dw02a
Contextual Info: i t IDT H IG H - S P E E D C T A T ir ^ d a u ^ L * P O R T S T A T IC R A M Featu res: * True Dual-Ported memory cells which allow simultaneous access of the same memory location * High-speed access - * industrial: 35ns max. Commercial: 15/2Q/25/35/55ns (max.)

Contextual Info: Full Duplex Technology, Incorporated Full Duplex CMOS Ethernet 10/100 Mega Bit/Sec Data Link Controller Preliminary _ April 19, 1996 Features • Low Power CMOS Technology ■ 10/100 MBit Ethernet Controller Optimized for Switching Hub, Multiport Bridge/Router,

Contextual Info: * L O W -R O W ER 9-BP SY N E R G Y S Y 100SJ21 IN VER TER S E M IC O N D U C T O R F EA TU R E S D E S C R IP TIO N • Max. propagation delay of 700ps The SY100S321 is a monolithic 9-bit inverter. The device contains nine inverting buffer gates with single