DELAY111 Search Results

84C300A

Contextual Info: Full Duplex 84C 300A 4-Port Fast Ethernet Controller Technology Incorporated PRELIMINARY _April 19, 1996 Features • Low Power CMOS Technology ■ 4-Port Ethernet Controller Optimized for Note: Check for latest Data Sheet revision

Contextual Info: « LOW-POWER HEX PECL-TO-TTL TRANSLATOR SYNERGY SEMICONDUCTOR FE A T U R E S PRELIMINARY SY100S390 DESCRIPTION The SY100S390 is a hex PECL-to-TTL translator for converting 100K logic levels to TTL logic levels. Unlike other level translators, the SY100S390 operates using only one

84C30A

Abstract: 051b3
Contextual Info: Full Duplex S4C30A 4-Port Technology Incorporated Ethernet Controller PRELIMINARY April 19, 1996 Features • ■ Note: Check for latest Data Sheet revision before starting any designs. Low Power CMOS Technology ■ Meets A NSI/IEEE802.3 and ISO 8802-3 Standards

SY-510

Abstract: 7006L 7006S
Contextual Info: OlDT HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM Features * * * * IDT7006S/L one d evice_ M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling