CYM74P55 Search Results

74555

Abstract: ZENER A17 LA17-LA5 CYM74B550 CYM74P550A CYM74S550 CYM74S551 74S551 OPTi viper
Contextual Info: ^ S T ñ u n n rn r CYM74B550 CYM74P550A CYM74S550, CYM74S551 PRELIMINARY •=•> y L- Ï i n L o b = OPTi Viper Chip Set Level II Cache Module Family volt SRAMs and 3.3 volt level translators. These modules offer 3-2-2-2 performance at CPU bus speeds up to 6 6 MHz.

Contextual Info: CYPRESS CYM74BP54 CYM74P54/55 CYM74SP54/55 PRELIMINARY Features • Pin-compatible secondary cache m odule fam ily • Asynchronous CYM74BP54 , synchronous pipelined (CYM74P54, CYM74P55), or synchronous (CYM74SP54, CYM74SP55) configurations with pres­ ence and configuration detect pins

ZENER A17

Abstract: A18A 3BE0 A17 ZENER diode ZENER A16 TAG 106 D sram 8kx8 cache
Contextual Info: 1CY M74 S55 0, CYM7 4S 551 CYM74B550 CYM74P550A CYM74S550, CYM74S551 PRELIMINARY OPTi Viper Chip Set Level II Cache Module Family Features volt SRAMs and 3.3 volt level translators. These modules offer 3-2-2-2 performance at CPU bus speeds up to 66 MHz. • Pin-compatible secondary cache module family

Contextual Info: CYPRESS CYM74B550 CYM74P550A CYM74S550, CYM74S551 P R E L IM IN A R Y OPTi Viper Chip Set Level II Cache Module Family Features vo lt S R A M s and 3.3 v o lt level translators. T hese m odules offer 3 -2 -2-2 pe rfo rm an ce at CPU bus speeds up to 6 6 MHz.

TU 55x

Abstract: NDM1-63 UEI 20 SP BA 9513
Contextual Info: CYM74B550 CYM 7 4 P 5 5 0 A C Y M 7 4 S 5 5 0 , CY M 7 4 S 5 5 1 OPTi Viper Chip Set Level II Cache Module Family vo lt S R A M s and 3.3 volt level translators. T hese m odules offer 3-2 -2-2 p e rfo rm an ce at GPU bus speeds up to 6 6 MHz. Features • Pi n- co mp a ti b le s e c on da ry c a c h e m o d u l e family

A5 GNC

Abstract: A1W 73 c877 A64A A1 GNC cym74sp55pm 82430NX CYM74BP54 CYM74P54 0/mosfet A5 GNC
Contextual Info: CYM74BP54 CYM74P54/55 CYM74SP54/55 æ r~ ^ S T •= • > y PRELIMINARY n u n n rn r L- Ï i n L o b = Intel 82430NX Chipset Level II Cache Module Family Features • Pin-compatible secondary cache module fam ily • Asynchronous CYM74BP54 , synchronous pipelined

ADU01

Abstract: Intel P55 Chipset D31CD
Contextual Info: — ^ C Y M 7 4 B P 5 4 CYM 74P54/55 ^ l r t î m n r n P R E L IM IN A R Y . n wm W U ir K fc b b C Y M 7 4 S P 5 4 /5 5 — Intel 82430NX Chipset Level II Cache Module Family Feat ures • Pi n- compat i bl e secondary cache mo d ul e family • As yn ch r o no u s CYM7 4BP5 4 , sync h r o no us pipelined

74P55

Abstract: LA17-LA5
Contextual Info: 1CY M74 SP5 4/55 CYM74BP54 CYM74P54/55 CYM74SP54/55 PRELIMINARY Intel 82430NX Chipset Level II Cache Module Family Features dustry standard 5V SRAMs and 3.3V level translators for CPU bus speeds up to 66 MHz. The CYM74BP54 is organized as 32K by 64-bits.

Triton P54C

Abstract: cy7c37128 62128 SRAM adapter 48-pin TSOP CY7C37192 CYM74P436 CY3501A CY7C37512 MIB 30 Product Selector Guide
Contextual Info: Product Selector Guide Fast Static RAMs Organization/Density Density X1 X4 X4 SIO X8 4K 7C147 2147 7C123 7C148 7C149 7C150 2148 2149 7C122 9122 93422 16K 7C167A 7C168A 7C128A 6116 64K to 72K 7C187 7C164 7C166 7C185 6264 7C182 256K to 288K 7C197 7C194 7C195