CY7C33S Search Results

Contextual Info: This is an abbreviated datasheet. Contact a Cypress representative for complete specifications. For new designs, please refer to the CY7C33S. CY7C330 CMOS Programmable Synchronous State Machine CYPRESS SEMICONDUCTOR Features Three separate clocks— two inputs,

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Contextual Info: I U J O J . / / 1 0 /9 1 Revision: Friday, March 2 6 ,1993b M fP ? 1993 CY7C335 7J s CYPRESS SEMICONDUCTOR Universal Synchronous EPLD construct very high performance state ma­ chines. The architecture of the CY7C335, consist­ ing of the user-configurable output macrocell, bidirectional I/O capability, input reg­

Contextual Info: CY7C335 / CYPRESS Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect m ultiplexer — Feed back multiplexer — Output enable OE multiplexer

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Contextual Info: P / CY7C335 CYPRESS Features • 100-MHz output registered operation • Twelve I/O macroceils, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect multiplexer — Feed back multiplexer — O utput enable OE multiplexer

Contextual Info: CYPRESS SEMICONDUCTOR ~ Features • 100-MHz output registered operation • TVelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect multiplexer — Feed back multiplexer — Output enable OE multiplexer

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Abstract: 7C33566 cy7c335
Contextual Info: fax id: 6018 CY7C335 V CYPRESS Universal Synchronous EPLD Features — 2-ns input set-up and 9-ns output register clock to output 100-MHz output registered operation Twelve I/O macrocells, each having: — Registered, three-state I/O pins — 10-ns input register clock to state register clock