CY7C1516V18 Search Results

CY7C1520V18-200BZXC

Abstract: CY7C1520V18-300BZC CY7C1518V18-300BZC CY7C1516V18 CY7C1518V18 CY7C1520V18 CY7C1527V18
Contextual Info: CY7C1516V18, CY7C1527V18 CY7C1518V18, CY7C1520V18 72-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency

Contextual Info: CY7C1516V18 CY7C1527V18 CY7C1518V18 CY7C1520V18 72-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 The CY7C1516V18, CY7C1527V18, CY7C1518V18, and CY7C1520V18 are 1.8V Synchronous Pipelined SRAM

CY7C1520V18-300BZC

Abstract: CY7C1516V18 CY7C1518V18 CY7C1520V18 CY7C1527V18
Contextual Info: CY7C1516V18, CY7C1527V18 CY7C1518V18, CY7C1520V18 72-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency

CY7C1516V18

Abstract: CY7C1518V18 CY7C1520V18 CY7C1527V18
Contextual Info: CY7C1516V18 CY7C1527V18 CY7C1518V18 CY7C1520V18 72-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 The CY7C1516V18, CY7C1527V18, CY7C1518V18, and CY7C1520V18 are 1.8V Synchronous Pipelined SRAM

CY7C1516V18

Abstract: CY7C1518V18 CY7C1520V18 CY7C1527V18 cy7c1520v18-200bzc
Contextual Info: CY7C1516V18 CY7C1527V18 CY7C1518V18 CY7C1520V18 PRELIMINARY 72-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9,4M x 18,2M x 36 • 250-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency

Contextual Info: CY7C1516V18 CY7C1518V18 CY7C1520V18 PRELIMINARY 72-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9,4M x 18,2M x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency

Contextual Info: THIS SPEC IS OBSOLETE Spec No: 38-05563 Spec Title: CY7C1516V18/CY7C1527V18/CY7C1518V18/ CY7C1520V18 72-MBIT DDR-II SRAM 2-WORD BURST ARCHITECTURE Sunset Owner: Anuj Chakrapani AJU Replaced by: None CY7C1516V18, CY7C1527V18 CY7C1518V18, CY7C1520V18 72-Mbit DDR II SRAM 2-Word

Contextual Info: CY7C1516V18 CY7C1527V18 CY7C1518V18 CY7C1520V18 72-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency

Contextual Info: CY7C1557V18 CY7C1548V18 CY7C1550V18 PRELIMINARY 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 72-Mbit density (8M x 9, 4M x 18, 2M x 36) • 300 MHz to 375 MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency

BV25

Abstract: CY7C129 CY7C130 CY7C131 CY7C132 EV25 ev18
Contextual Info: CY7C129*DV18/CY7C130*DV25 CY7C130*BV18/CY7C130*BV25/CY7C132*BV25 CY7C131*BV18 / CY7C132*BV18/CY7C139*BV18 CY7C191*BV18/CY7C141*AV18 / CY7C142*AV18/ CY7C151*V18 /CY7C152*V18 Errata Revision: *D March 04, 2008 RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata This document describes the DOFF issue for QDRII/DDRII, the Output Buffer, the JTAG and the DLL issue for

Contextual Info: CY7C1568V18 CY7C1570V18 PRELIMINARY 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • • • • 72-Mbit density (4M x 18, 2M x 36) 300 MHz to 400 MHz clock for high bandwidth 2-Word burst for reducing address bus frequency

Contextual Info: CY7C1577V18 CY7C1568V18 CY7C1570V18 PRELIMINARY 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 72-Mbit density (8M x 9, 4M x 18, 2M x 36) • 300 MHz to 400 MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency

CY7C1338-100AXC

Abstract: gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC
Contextual Info: CYPRESS / GALVANTECH # - Connect pin 14 FT pin to Vss CY7C1019BV33-15VC GS71108AJ-12 & - Does not support 1.8V I/O CY7C1019BV33-15VXC GS71108AGJ-12 * - Tie down extra four I/Os with resistor CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12

05564

Abstract: BV25 CY7C129 CY7C130 CY7C131 CY7C132 CY7C1422AV18 1428A
Contextual Info: CY7C129*DV18/CY7C130*DV25 CY7C130*BV18/CY7C130*BV25/CY7C132*BV25 CY7C131*BV18 / CY7C132*BV18/CY7C139*BV18 CY7C191*BV18/CY7C141*AV18 / CY7C142*AV18/ CY7C151*V18 /CY7C152*V18 Errata Revision: *C May 02, 2007 RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata This document describes the DOFF issue for QDRII/DDRII and the Output Buffer and JTAG issues for

Contextual Info: CY7C1548V18 CY7C1550V18 PRELIMINARY 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • • • • 72-Mbit density (4M x 18, 2M x 36) 300 MHz to 375 MHz clock for high bandwidth 2-Word burst for reducing address bus frequency

Contextual Info: CY7C1557V18 CY7C1548V18 CY7C1550V18 PRELIMINARY 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 72-Mbit density (8M x 9, 4M x 18, 2M x 36) • 300 MHz to 375 MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency