CY230 Search Results

Contextual Info: CY2304NZ Four Output PCI-X and General Purpose Buffer Four Output PCI-X and General Purpose Buffer Features Functional Description • One input to four output buffer/driver The CY2304NZ is a low-cost buffer designed to distribute high-speed clocks for PCI-X and other applications. The device

CY2305

Abstract: CY2308 CY2309
Contextual Info: fax id: 3614 CY2305 and CY2309 as PCI and SDRAM Buffers Introduction to Cypress Zero Delay Buffers What is a Zero Delay Buffer? A zero delay buffer is a device that can fan out 1 clock signal into multiple clock signals with zero delay and very low skew between the outputs. This device is well suited as a buffer for

CY2302

Abstract: CY2302SC-1 CY2302SC-1T CY2302SI-1 CY2302SI-1T CY2302SXC-1 CY2302SXC-1T CY2302SXI-1 CY2302SXI-1T schematic diagram for power line ac voltage condi
Contextual Info: CY2302 Frequency Multiplier and Zero Delay Buffer Features Table 1. Configuration Options • 90ps typical jitter OUT2 FBIN • 200ps typical jitter OUT1 OUT1 2 X REF REF OUT1 1 4 X REF 2 X REF OUT1 1 REF REF/2 OUT1 1 1 8 X REF 4 X REF OUT2 4 X REF 2 X REF

Contextual Info: CYPRESS CY2309NZ Nine Output, 3.3V SDRAM Buffer for 2 DIMMs or 4 SO-DIMMs Features Functional Description • One input to nine output buffer/driver • Supports two SDRAM DIMMs or four SO-DIMMs with one additional output for feedback to an external or chipset PLL

Contextual Info: CY2305 CY2309 PRELIMINARY CYPRESS Low-Cost 3.3V Zero Delay Buffer for PC and SDRAM ules and is available in a 16-pin SOIC package. The CY2305 is an 8-pin version of the CY2309. It accepts one reference input, and drives out five skew-controlled clocks. Both parts

CY2304NZ

Abstract: CY2304NZZC-1 CY2304NZZC-1T CY2304NZZI-1 CY2304NZZI-1T CY2304NZZXC-1 CY2304NZZXC-1T CY2304NZZXI-1 CY2304NZZXI-1T CY2304NZZXI
Contextual Info: CY2304NZ Four Output PCI-X and General Purpose Buffer Features Functional Description • One input to four output buffer/driver The CY2304NZ is a low-cost buffer designed to distribute high-speed clocks for PCI-X and other applications. The device operates at 3.3V and outputs can run up to 140 MHz.

CY2308SC-1H

Abstract: CY2308 CY2308-1 CY2308-1H CY2308-2 CY2308-3 CY2308-4 23086 REF05
Contextual Info: fax id: 3526 1CY 230 8 CY2308 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations, see “Available CY2308 Configurations” table • Multiple low skew outputs — Output-output skew less than 250 ps

CY23020-3

Abstract: CY23020LFI-3 CY23020LFI-3T
Contextual Info: CY23020-3 10-output, 400-MHz LVPECL Zero Delay Buffer Features • • • • • • • • • • Overview 400-ps max Total Timing Budget TTB window 10 LVPECL outputs 1 LVPECL differential input Selectable output frequency range from 100 to 400 MHz

CY2081

Abstract: CY2071A CY2305 CY2308 CY2308-1 CY2308-2 CY2308-3 CY2308-4 CY2309
Contextual Info: CY2308: Zero Delay Buffer Introduction to Cypress Zero Delay Buffers What is a Zero Delay Buffer? A zero delay buffer is a device that can fan out one clock signal into multiple clock signals with zero delay and very low skew between the outputs. This device is well suited for a variety of

CY2304

Abstract: CY2304-1 CY2304-2 CY2304SC CY2308 PST44 REF05
Contextual Info: CY2304 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations – see “Available Configurations” table • Multiple low-skew outputs — Output-output skew less than 200 ps

CY2305SZC-1H

Abstract: CY2305 CY2309 CY2309SC-1
Contextual Info: CY2305 CY2309 Low-cost 3.3V Zero Delay Buffer Features • 10-MHz to 100-/133-MHz operating range, compatible with CPU and PCI bus frequencies up to 100-/133-MHz frequencies, and have higher drive than the -1 devices. All parts have on-chip PLLs which lock to an

CY2309NZ

Abstract: CY2309NZSXI-1H CY2309NZSXI-1HT SZ16
Contextual Info: CY2309NZ Nine-Output 3.3V Buffer Features Functional Description • One-input to nine-output buffer/driver ■ Supports two DIMMs or four SO-DIMMs with one additional output for feedback to an external or chipset PLL ■ Low power consumption for mobile applications

CY2303

Abstract: CY2303SC CY2303SI CY2303SXC CY2303SXCT CY2303SXI
Contextual Info: CY2303 Phase-Aligned Clock Multiplier Features Functional Description • 3-multiplier configuration 1x, 2x, 4x Ref ■ 10 MHz to 166.67 MHz operating range (reference input from 10 MHz to 41.67 MHz) The CY2303 is a 3 output 3.3V phase-aligned system clock

CY2303

Abstract: CY2303SC CY2303SI
Contextual Info: 3 CY2303 Phase-Aligned Clock Multiplier Features Benefits • 3-multiplier configuration 1x, 2x, 4x Ref • Single phase-locked loop architecture 10 MHz to 166.67 MHz operating range reference input from 10 MHz to 41.67 MHz • Phase Alignment All outputs will have a consistent phase relationship with each

CY2308-2

Abstract: CY2907 AN1234 CY2071A CY2305 CY2308 CY2308-1 CY2308-3 CY2308-4 CY2309
Contextual Info: CY2308: Zero Delay Buffer AN1234 Introduction to Cypress Zero Delay Buffers What is a Zero Delay Buffer? A zero delay buffer is a device that can fan out one clock signal into multiple clock signals with zero delay and very low skew between the outputs. This device is well suited for a

CY23020-3

Abstract: CY23020LFI-3 CY23020LFI-3T
Contextual Info: CY23020-3 10-output, 400-MHz LVPECL Zero Delay Buffer Features • • • • • • • • • • Overview 400-ps max Total Timing Budget TTB window 10 LVPECL outputs 1 LVPECL differential input Selectable output frequency range from 100 to 400 MHz

5VOLT

Abstract: CY2305 CY2309 CY2308
Contextual Info: CY2305 and CY2309 as PCI and SDRAM Buffers Introduction to Cypress Zero Delay Buffers What is a Zero Delay Buffer? A zero delay buffer is a device that can fan out 1 clock signal into multiple clock signals with zero delay and very low skew between the outputs. This device is well suited as a buffer for

CY2308-1

Abstract: CY2308 CY2308-1H CY2308-2 CY2308-3 CY2308-4 REF05
Contextual Info: CY2308 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by ca­ pacitive load on FBK input • Multiple configurations, see “Available CY2308 Config­ urations” table • Multiple low skew outputs — Output-output skew less than 250 ps

Contextual Info: CY2305 CY2309 Low-Cost 3.3V Zero Delay Buffer Features • 10-MHz to 100-/133-MHz operating range, compatible with CPU and PCI bus frequencies • Zero input-output propagation delay • 60 ps typical cycle-to-cycle jitter high drive • Multiple low-skew outputs

CY2308E

Abstract: CY2308SXI
Contextual Info: CY2308 3.3 V Zero Delay Buffer Features The CY2308 has two banks of four outputs each that is controlled by the select inputs as shown in the table Select Input Decoding on page 3. If all output clocks are not required, Bank B is three-stated. The input clock is directly applied to the output for

CY23085

Contextual Info: CY2308 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations, see “Available CY2308 Configurations” table • Multiple low skew outputs — Output-output skew less than 200 ps

Contextual Info: CY2303 CY2303 Phase-Aligned System Clock Features Benefits • 3-multiplier configuration 1x, 2x, 4x Ref • Single phase-locked loop architecture 10 MHz to 166.67 MHz operating range reference input from 10 MHz to 41.67 MHz • Phase Alignment All outputs will have a consistent phase relationship with each

cy2304si-1t

Abstract: REF05
Contextual Info: CY2304 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input required to be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 250 ps, and output-to-output skew is guaranteed to be

74LS324

Abstract: Radicom V92TM-D 1J23A 85LD0128 AMD29F016 C3528 rtl8139dl reference design c7343 snorteland RJ113
Contextual Info: A B C D COM1 & 2 PARALLEL E SERIAL & PARALLEL INTERFACE CONNECTORS Sheet 10 SDRAM 32-128MB: ISSI IS42S32800B 4 VGA CONNECTOR LCD CONNECTOR & CONFIG. SWITCHES Sheet 17 Sheet 6 SYSTEM CLOCK GEN: CYPRESS CY2305 CY2292 4 COM2 Sheet 3 Sheet 18 RJ11 PHONE CONNECTOR