CY2304SC Search Results

CY2304SI-1

Abstract: CY2308SC-1H CY2308SI-2 IDT CROSS IDT MPC962308D-1H NB2304AI2D NB2304AC1D NB2304AC1HD NB2304AC2D NB2304AI1D
Contextual Info: ZERO DELAY BUFFER CROSS REFERENCE GUIDE ON Semiconductor NB2304AC1D NB2304AI1D NB2304AC1HD NB2304AI1HD NB2304AC2D NB2304AI2D CYPRESS CY2304SC-1 CY2304SI-1 na na CY2304SC-2 CY2304SI-2 NB2305AC1D NB2305AI1D NB2305AC1DT NB2305AI1DT NB2305AC1HD NB2305AI1HD NB2305AC1HDT

CY2304

Abstract: CY2304-1 CY2304-2 CY2304SC CY2308 PST44 REF05
Contextual Info: CY2304 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations – see “Available Configurations” table • Multiple low-skew outputs — Output-output skew less than 200 ps

cy2304si-1t

Abstract: REF05
Contextual Info: CY2304 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input required to be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 250 ps, and output-to-output skew is guaranteed to be

CY2304-1

Abstract: CY2304 CY2304-2 CY2304SC CY2308 REF05
Contextual Info: CY2304 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations – see “Available Configurations” table • Multiple low-skew outputs — Output-output skew less than 200 ps

Contextual Info: 4 CY2304 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations – see “Available Configurations” table • Multiple low-skew outputs — Output-output skew less than 200 ps

Contextual Info: CY2304 3.3 V Zero Delay Buffer 3.3 V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input ■ Multiple configurations ■ Multiple low-skew outputs ■ 10 MHz to 133 MHz operating range ■ 90 ps typical peak cycle-to-cycle jitter at 15 pF, 66 MHz

1H08S

Abstract: PI6C2405A-1HW ASM706CUA SOIC-6 microchip ADM809RAR ADM705AN MAX809SEUR T ASM5P2309-1H-16-S K7N163601B MAX810JEUR
Contextual Info: Supervisors Cross Reference Guide Alliance Maxim/Dallas IMP ASM1232LP DS1232LPS-2 IMP1232LP ASM1232LPCMA DS1232LP IMP1232LPCMA ASM1232LPEMA DS1232LP IMP1232LPEMA ASM1232LPN DS1232LP IMP1232LPN Analog Devices Micrel Microchip MIC1232N TC1232CPA - - - - - -

AN1234

Abstract: CY2304 CY2304-1 CY2304-2 CY2304SC CY2308 REF05
Contextual Info: CY2304 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input required to be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 250 ps, and output-to-output skew is guaranteed to be

REF05

Contextual Info: CY2304 3.3 V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input ■ Multiple configurations ■ Multiple low-skew outputs ■ 10 MHz to 133 MHz operating range ■ 90 ps typical peak cycle-to-cycle jitter at 15 pF, 66 MHz

AN1234

Abstract: CY2304 CY2304-1 CY2304-2 CY2304SI-2 CY2308 REF05
Contextual Info: CY2304 3.3 V Zero Delay Buffer 3.3 V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input ■ Multiple configurations ■ Multiple low-skew outputs ■ 10 MHz to 133 MHz operating range ■ 90 ps typical peak cycle-to-cycle jitter at 15 pF, 66 MHz

Contextual Info: CY2304 3.3 V Zero Delay Buffer 3.3 V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input ■ Multiple configurations The part has an on-chip phase-locked loop PLL that locks to an input clock presented on the REF pin. The PLL feedback is

marvel phy 88e1111 reference design

Abstract: Marvell 88E1111 layout guide SMD SOT23 transistor MARK Y2 88E1111 AN8077 smd k24 CW-P423-156.25MHZ C4161 BLM41PG600SN1L smd diode u1j
Contextual Info:  LatticeECP3 Serial Protocol Board – Revision D User’s Guide July 2010 Revision: EB44_01.3  Lattice Semiconductor LatticeECP3 Serial Protocol Board – Revision D User’s Guide Introduction The LatticeECP3 Serial Protocol Board referred to in this document as “SPB” allows designers to investigate and

lcmx01200c

Abstract: smd m21 sot23 fuse smd marking f5 marking w25 SMD smd diode U12 c526 LCMXO1200C-CSBGA132 npn transistor smd w19 transistor C535 SMD BGA 672 DRAWING SPI-M2564
Contextual Info:  LatticeECP2M PCI Express Solutions Board User’s Guide September 2008 Revision: EB33_01.0  LatticeECP2M PCI Express Solutions Board User’s Guide Lattice Semiconductor Introduction As PCI Express applications have emerged, the LatticeECP2M FPGA family has become a well-suited solution

CY2304-1

Abstract: CY2304 CY2304-2 CY2304SC CY2308 pst44 REF05
Contextual Info: CY2304 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations—see “Available Configurations” table • Multiple low-skew outputs • 10-MHz to 133-MHz operating range

Contextual Info: CY2304 3.3 V Zero Delay Buffer 3.3 V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input ■ Multiple configurations ■ Multiple low-skew outputs ■ 10 MHz to 133 MHz operating range ■ 90 ps typical peak cycle-to-cycle jitter at 15 pF, 66 MHz

TCO2111-245.76MHZ

Abstract: SMD SOT23 transistor MARK Y2 C4161 CW-P423-156.25MHZ smd sot23-3 W32 CMOS PLD Programming Hardware and Software Support 32K153-400L5 ROSENBERGER 32K153-400L5 ROHM capacitor 100nf 16v 1005 x7r CW-P423
Contextual Info:  LatticeECP3 Serial Protocol Evaluation Board – Revision D User’s Guide September 2009 Revision: EB44_01.1  LatticeECP3 Serial Protocol Evaluation Board – Revision D User’s Guide Lattice Semiconductor Introduction The LatticeECP3 Serial Protocol Evaluation Board referred to in this document as “SPB” allows designers to

CY2304SXI-1

Abstract: 450-mA CY2304SI-1T CY2304 CY2304-1 CY2304-2 CY2304SC CY2308 REF05
Contextual Info: CY2304 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations—see “Available Configurations” table • Multiple low-skew outputs • 10-MHz to 133-MHz operating range

AN1234

Abstract: CY2304 CY2304-1 CY2304-2 CY2304SC CY2308 REF05
Contextual Info: CY2304 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input required to be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 250 ps, and output-to-output skew

CY2304-1

Contextual Info: CY2304 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input • Multiple configurations, see “Available Configurations” table • Multiple low-skew outputs — Output-output skew less than 200 ps

Contextual Info: CY2304 3.3 V Zero Delay Buffer 3.3 V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by capacitive load on FBK input ■ Multiple configurations The part has an on-chip phase-locked loop PLL that locks to an input clock presented on the REF pin. The PLL feedback is