CUA877 Search Results

Contextual Info: CDCU2A877 www.ti.com SCAS827A – AUGUST 2006 – REVISED JUNE 2007 1.8-V PHASE LOCK LOOP CLOCK DRIVER • FEATURES • • • • • • • • • 1.8-V/1.9-V Phase Lock Loop Clock Driver for Double Data Rate DDR II Applications Spread Spectrum Clock Compatible

CSPUA877

Abstract: 2506036017Y0 CSPUA877A CUA877 IDTCSPUA877A
Contextual Info: IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER IDTCSPUA877A DESCRIPTION: FEATURES: The CSPUA877A is a PLL based clock driver that acts as a zero delay buffer

DDR2-400

Abstract: DDR2-533 DDR2-667 EBE20RE4ABFA EBE20RE4ABFA-4A-E EBE20RE4ABFA-5C-E EBE20RE4ABFA-6E-E CS 3820
Contextual Info: PRELIMINARY DATA SHEET 2GB Registered DDR2 SDRAM DIMM EBE20RE4ABFA 256M words x 72 bits, 1 Rank Specifications Features • Density: 2GB • Organization  256M words × 72 bits, 1 rank • Mounting 18 pieces of 1G bits DDR2 SDRAM sealed in FBGA • Package: 240-pin socket type dual in line memory

EBE10AD4AGFA-6E-E

Abstract: DDR2-400 DDR2-533 DDR2-667 EBE10AD4AGFA EBE10AD4AGFA-4A-E EBE10AD4AGFA-5C-E E0865E11
Contextual Info: PRELIMINARY DATA SHEET 1GB Registered DDR2 SDRAM DIMM EBE10AD4AGFA 128M words x 72 bits, 1 Rank Specifications Features • Density: 1GB • Organization  128M words × 72 bits, 1 rank • Mounting 18 pieces of 512M bits DDR2 SDRAM sealed in FBGA • Package: 240-pin socket type dual in line memory

DDR2-667

Abstract: EDE5104AJSE-8E-E udqs
Contextual Info: PRELIMINARY DATA SHEET 2GB Registered DDR2 SDRAM DIMM EBE21AD4AJFA 256M words x 72 bits, 2 Ranks Specifications Features • Density: 2GB • Organization  256M words × 72 bits, 2 ranks • Mounting 36 pieces of 512M bits DDR2 SDRAM sealed in FBGA • Package: 240-pin socket type dual in line memory

DDR2-667

Abstract: EDE5104AJSE-8E-E EBE10AD4AJFA-6E-E max1546
Contextual Info: PRELIMINARY DATA SHEET 1GB Registered DDR2 SDRAM DIMM EBE10AD4AJFA 128M words x 72 bits, 1 Rank Specifications Features • Density: 1GB • Organization  128M words × 72 bits, 1 rank • Mounting 18 pieces of 512M bits DDR2 SDRAM sealed in FBGA • Package: 240-pin socket type dual in line memory

DDR2 DIMM 240 pin names

Abstract: DDR2-667 EDE5104AJSE-8E-E EBE21AD4AJFA-6E-E EBE21AD4AJFA 2843ps
Contextual Info: DATA SHEET 2GB Registered DDR2 SDRAM DIMM EBE21AD4AJFA 256M words x 72 bits, 2 Ranks Specifications Features • Density: 2GB • Organization  256M words × 72 bits, 2 ranks • Mounting 36 pieces of 512M bits DDR2 SDRAM sealed in FBGA • Package: 240-pin socket type dual in line memory

DDR2-667

Abstract: EDE1108ACSE-6E-E
Contextual Info: DATA SHEET 4GB Registered DDR2 SDRAM DIMM EBE42AE8ACFA 512M words x 72 bits, 4 Ranks Specifications Features • Density: 4GB • Organization  512M words × 72 bits, 4 ranks • Mounting 36 pieces of 1G bits DDR2 SDRAM sealed in FBGA • Package: 240-pin socket type dual in line memory

E0901E20

Abstract: EBE41AE4ABHA DDR2-667
Contextual Info: DATA SHEET 4GB Registered DDR2 SDRAM DIMM EBE41AE4ABHA 512M words x 72 bits, 2 Ranks Specifications Features • Density: 4GB • Organization  512M words × 72 bits, 2 ranks • Mounting 36 pieces of 1G bits DDR2 SDRAM with sFBGA • Package: 240-pin socket type dual in line memory

DDR2-667

Abstract: EBE21RD4AEFA EDE5104AESK-6E-E
Contextual Info: DATA SHEET 2GB Registered DDR2 SDRAM DIMM EBE21RD4AEFA-6 256M words x 72 bits, 2 Ranks Features The EBE21RD4AEFA is a 256M words × 72 bits, 2 ranks DDR2 SDRAM Module, mounting 36 pieces of 512M bits DDR2 SDRAM sealed in FBGA package. Read and write operations are performed at the cross

Contextual Info: CDCU2A877 www.ti.com SCAS827A – AUGUST 2006 – REVISED JUNE 2007 1.8-V PHASE LOCK LOOP CLOCK DRIVER • FEATURES • • • • • • • • • 1.8-V/1.9-V Phase Lock Loop Clock Driver for Double Data Rate DDR II Applications Spread Spectrum Clock Compatible

Contextual Info: IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER IDTCSPUA877A FEATURES: DESCRIPTION: • 1 to 10 differential clock distribution • Optimized for clock distribution in DDR2 Double Data Rate

CSPUA877

Contextual Info: IDTCSPUA877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER IDTCSPUA877 FEATURES: DESCRIPTION: • 1 to 10 differential clock distribution • Optimized for clock distribution in DDR2 Double Data Rate

VFQFPN 28

Contextual Info: IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER IDTCSPUA877A DESCRIPTION: FEATURES: The CSPUA877A is a PLL based clock driver that acts as a zero delay buffer

DDR2-400

Abstract: DDR2-533 DDR2-667 EBE10RD4AJFA EBE10RD4AJFA-4A-E EBE10RD4AJFA-5C-E EBE10RD4AJFA-6E-E max1546
Contextual Info: DATA SHEET 1GB Registered DDR2 SDRAM DIMM EBE10RD4AJFA 128M words x 72 bits, 1 Rank Specifications Features • Density: 1GB • Organization  128M words × 72 bits, 1 rank • Mounting 18 pieces of 512M bits DDR2 SDRAM sealed in FBGA • Package: 240-pin socket type dual in line memory

Contextual Info: PRELIMINARY DATA SHEET 8GB Registered DDR2 SDRAM DIMM EBE81AF4ABHA 1024M words x 72 bits, 2 Ranks Specifications Features • Density: 8GB • Organization  1024M words × 72 bits, 2 ranks • Mounting 36 pieces of 2G bits DDR2 SDRAM with sFBGA • Package: 240-pin socket type dual in line memory

293ps

Contextual Info: PRELIMINARY DATA SHEET 2GB Registered DDR2 SDRAM DIMM EBE21AD4AJFA 256M words x 72 bits, 2 Ranks Specifications Features • Density: 2GB • Organization  256M words × 72 bits, 2 ranks • Mounting 36 pieces of 512M bits DDR2 SDRAM sealed in FBGA • Package: 240-pin socket type dual in line memory

Contextual Info: DATA SHEET 2GB Registered DDR2 SDRAM DIMM EBE21RD4AEFA-6 256M words x 72 bits, 2 Ranks Description Features The EBE21RD4AEFA is a 256M words × 72 bits, 2 ranks DDR2 SDRAM Module, mounting 36 pieces of 512M bits DDR2 SDRAM sealed in FBGA (µBGA) package. Read and write operations are performed at

Contextual Info: PRELIMINARY DATA SHEET 4GB Registered DDR2 SDRAM DIMM EBE41AE4ACFA 512M words x 72 bits, 2 Ranks Specifications Features • Density: 4GB • Organization  512M words × 72 bits, 2 ranks • Mounting 36 pieces of 1G bits DDR2 SDRAM sealed in FBGA • Package: 240-pin socket type dual in line memory

Contextual Info: PRELIMINARY DATA SHEET 4GB Registered DDR2 SDRAM DIMM EBE41RE4ACFA 512M words x 72 bits, 2 Ranks Specifications Features • Density: 4GB • Organization  512M words × 72 bits, 2 ranks • Mounting 36 pieces of 1G bits DDR2 SDRAM sealed in FBGA • Package: 240-pin socket type dual in line memory

Contextual Info: PRELIMINARY DATA SHEET 1GB Registered DDR2 SDRAM DIMM EBE10AD4AJFA 128M words x 72 bits, 1 Rank Specifications Features • Density: 1GB • Organization ⎯ 128M words × 72 bits, 1 rank • Mounting 18 pieces of 512M bits DDR2 SDRAM sealed in FBGA • Package: 240-pin socket type dual in line memory

EDE1116ACSE

Abstract: DDR2-667 DDR2-800
Contextual Info: DATA SHEET 4GB Registered DDR2 SDRAM DIMM EBE41AE4ACFA 512M words x 72 bits, 2 Ranks Specifications Features • Density: 4GB • Organization  512M words × 72 bits, 2 ranks • Mounting 36 pieces of 1G bits DDR2 SDRAM sealed in FBGA • Package: 240-pin socket type dual in line memory

DDR2-667

Abstract: DDR2-800
Contextual Info: DATA SHEET 1GB Registered DDR2 SDRAM DIMM EBE10AE8ACWA 128M words x 72 bits, 1 Rank Specifications Features • Density: 1GB • Organization  128M words × 72 bits, 1 rank • Mounting 9 pieces of 1G bits DDR2 SDRAM sealed in FBGA • Package: 240-pin socket type dual in line memory

INCUA877

Abstract: YX 805 4 pin INCUA877-GS04 yx 805 INCU877 INCUA878 INCUA877-GS50 82.XX.8 DDR2-400 DDR2-533
Contextual Info: INCU877, INCU878 CUA877, INCUA878, INCU2A877 DDR2 1:10 Zero Delay Clock Buffer Data Sheet Applications • • • DDR2-400, 533, 667, and 800 Registered DIMMs High Performance Workstations Mid and High Performance Servers Features • • • • • •