CQ 455 Search Results

Content Addressable Memory

Abstract: "Content Addressable Memory" ternary content addressable memory IDT75K52134 Ternary CAM IDT75K62134 idt cam QDR cypress ternary
Contextual Info: Product Brief IDT75K52134 IDT75K62134 4.5M and 9M Network Search Engine NSE with QDR Interface To request the full datasheet, please contact your local IDT Sales Representative or call 1-831-754-4555 Introduction Device Description Evolving network speeds require critical functions such as forwarding

Content Addressable Memory

Abstract: ternary content addressable memory QDR cypress "Content Addressable Memory" idt cam IDT75K52134 IDT75K62134 IXP2400 IXP2800 ternary
Contextual Info: Product Brief IDT75K52134 IDT75K62134 4.5M and 9M Integrated IP Co-Processors IIPC with QDR Interface To request the full product brief, please contact your local IDT Sales Representative or call 1-831-754-4555 Introduction Device Description Evolving network speeds require critical functions such as forwarding

Content Addressable Memory

Abstract: "Content Addressable Memory" Ternary CAM ternary content addressable memory
Contextual Info: Product Brief IDT75K52134 IDT75K62134 4.5M and 9M Integrated IP Co-Processors IIPC with QDR Interface To request the full product brief, please contact your local IDT Sales Representative or call 1-831-754-4555 Introduction Device Description Evolving network speeds require critical functions such as forwarding

CV7105

Contextual Info: NJM2247A/B mu m If l- NJM2247A/B i, ts ^5 — 7.— A — f >/1? — K (Y , T*To 7 - f y ^ l / 3 > ij, Y, ^ - T .A V R-Y, R-Y, X-<n&WM B-Y hP — =fc B - Y il- t ^ if ib t iS f o K T 'O T f f - t M S C J : U, fcnTtiC L T l ' i t . tt HJH2247ANI/BM • 5 V # .—

PD44647186AF5-E22-FQ1-A

Abstract: PD44647366AF5-E25-FQ1-A
Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT PD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A 72M-BIT QDRTM II+ SRAM 2.0 & 2.5 CLOCK CYCLES READ LATENCY 4-WORD BURST OPERATION Description The μPD44647094A-A and μPD44647096A-A are 8,388,608-word by 9-bit, the μPD44647184A-A and μPD44647186A-A

Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT PD44646187A-A 72M-BIT DDR II+ SRAM SEPARATE I/O 2.5 CLOCK CYCLES READ LATENCY 2-WORD BURST OPERATION Description The μPD44646187A-A is 4,194,304-word by 18-bit synchronous double data rate static RAM fabricated with advanced

PD44647366AF5-E22-FQ1-A

Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid

Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid

Contextual Info: CY7C1510JV18, CY7C1525JV18 CY7C1512JV18, CY7C1514JV18 72-Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions ■ 267 MHz Clock for High Bandwidth ■

CY7C1510JV18

Abstract: CY7C1512JV18 CY7C1514JV18 CY7C1525JV18
Contextual Info: CY7C1510JV18, CY7C1525JV18 CY7C1512JV18, CY7C1514JV18 72-Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 267 MHz clock for high bandwidth ■

CY7C1512JV18

Abstract: CY7C1514JV18 CY7C1525JV18
Contextual Info: CY7C1525JV18 CY7C1512JV18 CY7C1514JV18 72-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions ■ 267 MHz Clock for High Bandwidth CY7C1525JV18 – 8M x 9

CY7C1512JV18

Abstract: CY7C1514JV18 CY7C1525JV18
Contextual Info: CY7C1525JV18 CY7C1512JV18 CY7C1514JV18 72-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions ■ 267 MHz Clock for High Bandwidth CY7C1525JV18 – 8M x 9

Contextual Info: THIS SPEC IS OBSOLETE Spec No: 001-14435 Spec Title: CY7C1525JV18 CY7C1512JV18 CY7C1514JV18, 72-MBIT QDR R II SRAM 2-WORD BURST ARCHITECTURE Sunset Owner: Anuj Chakrapani (AJU) Replaced by: None CY7C1525JV18 CY7C1512JV18 CY7C1514JV18 72-Mbit QDR II SRAM 2-Word Burst

gs8182q36

Contextual Info: GS8182Q18/36D-200/167/133 18Mb Burst of 2 SigmaQuad-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 200MHz–133MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface

d1943g

Abstract: PD1943 PD6120 HPD-61
Contextual Info: MOS INTEGRATED CIRCU IT , / ¿ P D 6 1 2 1 „.• D ■T! Pint >Kitsnoiefi aimçmO Î? two or,tOM»ito?Vi art1 tte>' M U L T I- P U R P O S E R EM O T E C O N T R O L T R A N S M IT T E R 1C C M O S LS I D ESCRIPTIO N The ¿¿PD6121 is an infrared remote control transmitter LSI for T V , V C R , stereo components, cassette decks, air con­

Contextual Info: GS8182Q18/36D-200/167/133 200MHz–133MHz 1.8 V VDD 1.8 V and 1.5 V I/O 18Mb Burst of 2 SigmaQuad-II SRAM 165-Bump BGA Commercial Temp Industrial Temp SigmaRAM Family Overview Bottom View 165-Bump, 13 mm x 15 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array JEDEC Std. MO-216, Variation CAB-1

Contextual Info: GS8182Q18/36D-200/167/133 18Mb Burst of 2 SigmaQuad-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 200MHz–133MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface

uPD6120

Abstract: npd19 KL SN 102 PD1913 Li42 UD1943 ud271 27S9S KL 13 diode UPD6120C102
Contextual Info: MOS DIGITAL INTEGRATED CIRCU IT /¿ P D 6 1 2 0 M U L T I- P U R P O S E R E M O T E C O N T R O L T R A N S M IT T E R IC C M O S LSI D ESCRIPTIO N The pPD6120 is an LSI for the transmission of general-purpose, infrared, remote control codes to TV s, V TR s, audio equip­

HOA0825-4

Abstract: HOA0825-1 HOA0825-3 HOA0825-2 7N55 6n55 2N55 HOA0825 1T55 5T55
Contextual Info: HONEYWELL INC/ MICRO M1E D • 4551330 0013fl75 1 *HONl T - Ml-73 Transmissive With Plastic Encapsulated Components Assemblies Assem blies on this page are based on plastic-encapsulated components from the SEP8506 and SDP8406 device fam ilies. All sensors are phototransistors.

Contextual Info: GS8182T19/37BD-435/400/375/333/300 18Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR-II Interface • Common I/O bus • JEDEC-standard pinout and package

Contextual Info: GS8182T19/37BD-435/400/375/333/300 18Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR-II Interface • Common I/O bus • JEDEC-standard pinout and package

GS818

Contextual Info: GS8182T19/37BD-435/400/375/333/300 18Mb SigmaCIO DDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 435 MHz–300 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus

RAM32M

Abstract: RAM64X1D SRLC32E RAM128X1D RAM256X1S SRL32 RAM64M ROM64x1 XC6VLX75T ROM256x1
Contextual Info: Virtex-6 FPGA Configurable Logic Block User Guide Virtex-6 FPGA CLB [optional] UG364 v1.1 September 16, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development

BW110

Contextual Info: Preliminary GS8182T19/37BD-450/435/400/375/333/300 18Mb SigmaCIO DDR-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 450 MHz–300 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaCIO Interface