CODE AVW Search Results

Contextual Info: Temic TSC80251G1D Semiconductors Extended 8-bit Microcontroller with Serial Communication Interfaces 1. Description to 256 Kbytes of external code and data. Additionally, the TSC83251G1D provides on-chip code memory 16 Kbytes ROM . The TSC80251G1D products are derivatives of the

MA2Q738

Abstract: MA738
Contextual Info: Regulations No.: IC3F5090 Total Pages Page 15 1 Part No. AN8016NSH-A Package Code No. SSOP010-P-0225A Semiconductor Company Matsushita Electric Industrial Co., Ltd. Established by k. oU'i Applied by Checked by Prepared by M.Hiramatsu M.Yamanaka M.Motomori

1607b

Abstract: C1039 C513 SAB-C513A-L16P "C513A-L16P" CPU 103 siemens Marking AD6 siemens crystal clock
Contextual Info: SIEMENS This Material Copyrighted By Its Respective Manufacturer SAB-C513A-L16P 16 MHz Specification SIEMENS Ordering Information Type Ordering Code Package Description 8-Bit CMOS Microcontroller SAB-C513A-L16P Q 67120-C1039 P-DIP-40 for external memory, 16 MHz

80c251 assembler

Abstract: microcontroller 87C251 272616 80C251 manual
Contextual Info: intèl  O W ÂN IgiB ONF@I^IMIÂTrD@M 8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER Commercial Binary-code Compatible with MCSP 51 Microcontrollers Pin Compatible with 44-lead PLCC MCS 51 Microcontrollers Register-based MCS 251 Architecture

4a2l

Contextual Info: PRELIMINAR in te i 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Commercial/Express • Real-time and Programmed Wait State Bus Operation ■ User-selectable Configurations: — External Wait States 0-3 wait states ■ Binary-code Compatible with MCS> 51

Contextual Info: PRELIMINARY in te i 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Commercial/Express • User-selectable Configurations: — External Wait States 0-3 wait states ■ Real-time and Programmed Wait State Bus Operation ■ Binary-code Compatible with MCS> 51

272788

Contextual Info: ADVANCE INFORMATION in te i 83C196EA CHMOS 16-BIT MICROCONTROLLER Automotive Serial debug unit provides read and write access to code RAM with no CPU overhead • 40 MHz operation ■ Optional clock doubler ■ 2 Mbytes of linear address space Chip-select unit CSU

intel 27135

Contextual Info: a p m m i in te l ! oKHF@osiKDÆiroia>M M87C251SB 8-BIT MICROCONTROLLER WITH 16 KBYTES USER PROGRAMMABLE EPROM Military Binary-code Compatible with MCS 51 Microcontrollers Pin Compatible with 44-lead PLCC MCS 51 Microcontrollers Register-based MCS 251 Architecture

80C251TB24

Abstract: A5001 A4532-02
Contextual Info: ADVANCE INFORMATION 8xC251 TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Commercial/Express • Real-time and Programmed W ait State Bus Operation ■ Binary-code Com patible with MCSf 51 ■ Pin Com patible with 44-pin PLCC and 40-pin PDIP MCS 51 Sockets

80C251TB24

Contextual Info: 8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 1.0 INTRODUCTION A member of the Intel family of 8-bit MCS 251 micro­ controllers, the 8xC251TA/TB/TP/TQ is binary-code compatible with MCS 51 microcontrollers and pin compatible with 40-pin PDIP and 44-pin PLCC

A4213

Abstract: intel embedded microcontroller handbook a4118 intel 27135 a5093
Contextual Info: PRODUCT PREVIEW in te l M87C251 SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER Military • Real-time and Programmed Wait State Bus Operation ■ Binary-code Compatible with MCS> 51 ■ Pin Compatible with 44-pin PLCC and 40pin PDIP MCS 51 Sockets ■ Register-based MCSl® 251 Architecture

29LV800

Abstract: psop 08
Contextual Info: Advance information Features •Organization: 1M x 8 / 5 12 K x 1 6 • Sector architecture - One 16K; two 8K; one 32K; and fifteen 64K byte sectors - One 8K; two 4K; one 16K; and fifteen 32K word sectors - Boot code sector architecture— T top or B (bottom)

transistor bl p81

Abstract: transistor bl p87
Contextual Info: [p[F3 [0> !J T [PIFSEVOE^ in y 83C196EA CHMOS 16-BIT MICROCONTROLLER Automotive 32 MHz operation Optional clock doubler 2 Mbytes of linear address space 1 Kbyte of register RAM 3 Kbytes of code RAM 8 Kbytes of ROM Register-to-register architecture Stack overflow/underflow monitor with

Contextual Info: SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR S G U S 0 2 0 - JUNE 1996 Military Operating Temperature Range: - 55°C to 125°C HFG PA CKAGE TO P V IE W Processed to MIL-PRF-38535 Fast Instruction Cycle Time (30 ns and 40 ns) Source-Code Compatible With All ’C1x

Contextual Info: A Advance information •■ AS29LV800 3V 1MX8/512KX16 CMOS Flash EEPROM Features • Organization: 1Mx 8/512K x 16 • Scctor architecture - One 16K; two 8K; one 32K; and fifteen 64Kbyte sectors - One 8K; two 4K; one 16K; and fifteen 32Kword sectors - Boot code sector architecture—T top or B (bottom)

Contextual Info: 12/18/2003 09:53 FAI 2194774856 OKAYA ELECTRIC @001 OKAYA ELECTRIC AMERICA, INC. 503 WALL STREET, VALPARAISO, INDIANA 46383 TEL; 219-477-448B FAX: 219-477-4856 Ini"! i'.'i'iVilï.ÏMmf WW UnWWW, «lVn- Ti';' '.VV!1: CUSTOMER SA M PLE CODE ffhl-ij Coó-i wtít bechirgsd'»vivi;-

Contextual Info: Preliminary information •■ AS29LV002 3V 256Kx8 CMOS Flash EE PROM Features • O rganization: 256K x8 • Sector architecture - O ne 16K; tw o 8K; one 32K; and three 64K byte sectors - Boot code sector architecture— T top or B (bottom ) - Erase any com bination o f sectors or full chip

Contextual Info: A Advance information •■ AS29LV800 3V 1MX8/512KX16 CMOS Flash EEPROM Features • Organization: 1Mx 8/512K x 16 • Scctor architecture - One 16K; two 8K; one 32K; and fifteen 64Kbyte sectors - One 8K; two 4K; one 16K; and fifteen 32Kword sectors - Boot code sector architecture—T top or B (bottom)

Contextual Info: Order this document by 3VFPMU72D/D MOTOROLA SEMICONDUCTOR TECHNICAL DATA 4M X 72 3.3 V, FPM, Unbuffered D R A M D u al-In -L in e M em ory M odule D IM M 32 Megabyte for Error Correction Code Applications • JEDEC-Standard 168-Lead D ual-ln-Line Memory Module (DIMM)

5962-8601501XX

Abstract: 07263 CAGE CODE 5962-8601503XX IDT7187S55LB IMS1601S-55LM IMS1601S70LM UAA 1006
Contextual Info: REVISIONS DATE YR-MO-DA DESCRIPTION LTR Add fiv e vendors, CAGE 61772, CAGE 04713, CAGE 60991, CAGE 50088, and CAGE 65786. Add 04 new device typ e s. Add case o u tlin e l e t t e r Y. APPROVED 1988 JUNE 17 CURRENT CAGE CODE 67268 REV SHEET REV SHEET A A

TGAM 1

Abstract: P1240A
Contextual Info: 8 0 C 1 9 6 E A C H M O S 1 6 - BI T MICROCONTROLLER Commercisi P r e l im in a r y Datasheet Product Features a 40 MHz Operation & Optional Clock Doubler 2 Mbytes of Linear Address Space 8 1 Kbyte of Register RAM 3S 3 Kbytes of Code RAM S3 Register-Register Architecture

MIL-R-5847

Contextual Info: MFG. IDEHT. CODE #95077 MECHANICAL .4-3 7 A C R O S S FLATS HOLES 3 ,033D)A,WlREL0fK ¡20° a p a r t CgBUES RG—122 1 . M aterials A ll m etal p a rts except outer, contact and lock ring l/2 Hard Brass p er QQ-B-626, Cco|?. 22. Outer contact - Beryllium Copper per QQ-C-530,

Contextual Info: H igh p erform ance 256KX8 3V CMOS Flash EEPROM H AS29LV002 A 2S6KX8 CMOS Flash EEPROM Prelim inary inform ation Features • O rg a n iz a tio n : 256 K X 8 • S ecto r a rc h ite c tu re - O ne 16K; tw o 8K; one 32K; and three 64K byte sectors - Boot code sector architecture— T top o r B (bottom )

29f200-90

Abstract: AS29F200T
Contextual Info: Preliminary information Features • O r g a n iz a tio n : 2 5 6 K x 8 o r 1 2 8 K X 1 6 • L o w p o w e r c o n s u m p t io n • S e c to r a rc h ite c tu re - O ne 16K; tw o 8K; one 32K ; and three 64K byte sectors - Boot code sector architecture— T top or B (b o ttom )