CENTER Search Results

7408, 7404, 7486, 7432

Abstract: RF400U functional diagram of 7400 and cd 4011 ls 7404 180 nm CMOS standard cell library TEXAS INSTRUMENTS 74191 4BITS s273 buffer 74374 7408 CMOS cmos 7404
Contextual Info: TGC100 Series CMOS Gate Arrays RELEASE 3.0, REVISED JANUARY 1990 • Twelve Arrays with up to 26K Available Gates • Fast Prototype Turnaround Time • Extensive Design Support - Design Libraries Compatible with Daisy, Valid, and Mentor CAE Systems - Tl Regional ASIC Design Centers

Contextual Info: 54AC11032, 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TI0060— D2957, JULY 1987— REVISED MARCH 1990 54A C 11032 . . . J PACKAGE 74A C 11032 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin V c c and GND Configurations to

Contextual Info: 54AC11021,74AC11021 DUAL 4-INPUT POSITIVE-AND GATES _ D2957. JULY 1987 - REVISED APRIL 1993 54AC11021 . . . J PACKAGE 74AC11021 . . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations

Contextual Info: 54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES D2957, JUNE 1987 - REVISED APRIL 1993 54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin Vcc and GND Configuration Minimizes High-Speed Switching Noise

Contextual Info: BUCHANAN Catalog 1308389 Terminal Blocks Revised 12-02 TW O-PIECE TERM IN AL B L O C K C O N N EC TO R S 14.4 max. Straight, Closed End Headers, w'Ejectors, 5.08 mm Centerline C o lo r-G re e n .567 12.25 min. A52 H UL R a tin g -3 0 0 V, 15 A 9J5 nhTt Ji

Contextual Info: 54ACT11002,74ACT11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCAS003A - D2957, JUNE 1987 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-PIn V^c and GND Configurations Minimize High-Speed Switching Noise

321f

Contextual Info: Catalog 1308389 BUCHANAN Terminal Blocks Revised 12-02 TWO-PIECE TERM INAL BLOCK CONNECTORS Straight, Open End Headers, 7.62 mm Centerline Color-Green UL Rating-3 0 0 V, 15 A Z.91 .115 ' J U u 1.U 7,62 C39 R ecom m ended PC Board Layout .300 0 1 .4 o 7.62

55B8

Abstract: a 1524 b2859
Contextual Info: Catalog 1308389 BUCHANAN Terminal Blocks Revised 12-02 BOARD MOUNT, SIDE WIRE ENTRY Board Mount 10.16 mm Centerline, Side WirB Entry C o lo r-G re e n UL R a t in g -6 0 0 V, 17.5 A 12 30 AWG 15 A for field wiring applications • a 1 .4 i f t l y 10.16 .400

D2957

Contextual Info: 54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS I_ • ■ I I I D2957, JULY 1987-R E V IS E D APRIL 1993 * 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations

Contextual Info: RECTIFIERS SES5601C SES5602C SES5603C High Efficiency, 25A Center-Tap FEATURES • Low Forward Voltage • Fast Switching Speed • Convenient Package • High Surge Capability • Low Thermal Resistance • Mechanically Rugged TO-3 Package • Available as Positive or Negative Center-Tap

74AC11520

Contextual Info: 54AC11520,74AC11520 8-BIT IDENTITY COMPARATORS D2957, JULY 1987 - REVISED APRIL 1993 54AC11520 . . . J PACKAGE 74AC11S20. . . DW OR N PACKAGE TOP VIEW Compares TVvo 8-Bit Words Flow-Through Architecture Optimizes PCB Layout Center-PIn Vcc and GND Configurations

2a117

Contextual Info: 54AC11158, 74AC11158 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS TI010&— D 2957 JULY 1969— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11158 . . . J PACKAGE 74AC11158 . . . DW OR N PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to

Contextual Info: BUCHANAN Catalog 1308389 T e rm in al Blocks Revised 12-02 TWO-PIECE TERMINAL BLOCK CONNECTORS Stacking Plug, Rjght-Angle with Interlock, 5.0 mm Centerline Color-Green UL Rating - 300 V, 15 A 12-30 AWG Suggested Screw Torque— 7.0 in .-lb No. of Positions

Contextual Info: 74ACT11132 QUADRUPLE POSITIVE-NAND GATE WITH SCHMITT-TRIGGER INPUTS SCAS177 - D3974, JANUARY 1992 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Center-Pin V^c and GND Pin Configurations Minimize High-Speed Switching Noise EP/C Enhanced-Performance Implanted

Contextual Info: BUCHANAN Catalog 1308389 Terminal Blocks Re vised 12-02 TW O-PIECE TERMINAL B LO C K CO NN EC TO RS Straight Header w/Locking Screw Flange, 5.0 mm Centerline, Color - Green Recommended PC Board Layout 5.00 UL Rating -300 V, 15 A No. of Positions Dim. A 2 5.0 [0.197]

Contextual Info: 54AC 11004, 74AC11004 HEX INVERTERS TI0044— D2957, FEBRUARY 1068— REVISED M ARCH 1990 54AC11004 . . . J PACKAGE 74AC11004 . . . DW OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin Vq c and GND Configurations to

Contextual Info: BUCHANAN Catalog 1308389 Terminal Blocks R e v ise d 12-02 BOARD MOUNT, THREE-LEVELS STACKING CONNECTORS Board Mount w/lnterlock 5.0 mm Centerline, Three Levels, Stacking C o lo r-G re e n UL R atin g- 3 0 0 V, 24 A 12-30 AWG Wire Entry 20 A for Held wiring applications

TI009

Contextual Info: 54AC11643, 74AC 11643 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS T I0095— D2957, JU LY 1987— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11643 . . . JT PACKAGE 74AC11643 . . . DW OR NT PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to

D2957

Abstract: 1987-REVISEDAPRIL
Contextual Info: 54ACT11030,74ACT11030 8-INPUT POSITIVE-NAND GATES _ D2957. MARCH 1987-REVISEDAPRIL 1993 Inputs Are TTL*Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-PIn V^c and GNO Configurations Minimize High-Speed Switching Noise EPIC Enhanced-Perlormance Implanted

74AC108

Abstract: so 54 t 74AC11066
Contextual Info: 54AC11086, 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES TI0152— D3375, N O VEM BER 1989 • Flow-Through Architecture to Optimize PCB Layout 54AC11086 . . . J PACKAGE 74AC11086 . . . D OR N PACKAGE TOP VIEW • Center-Pin Vqc and GND Configurations to

1202J

Contextual Info: BUCHANAN Catalog 1308389 Terminal Blocks Revised 12-02 B O A R D MOUNT, SIDE WIRE ENTRY Board Mount, 2.54 mm Centerline, Side Wire Entry J UL R ating-150 V, 10 A 16-30 AWG V le s t Facility 'C la m p in g S c re w 1.25 R e com m en ded P C B oard Layo u t

3D16A-P

Abstract: F14GB-P F14G 3D16A 6D28A-P
Contextual Info: D I P - 8 P I N O U T L I N E DRAWING 3D8A-P U n it i n mm i~i r~I I—I + 0.1 0-Ä5-0.0 5 Note) Lead pitch is 2.54 and tolerance is ±0.25 against theoretical center of each lead that is obtained on the b asis of N o . l and N o . 14 leads. 651 DI P 16 P I N O U T L I N E DRAWING

74690

Abstract: 74692 8Q21
Contextual Info: TFyAi TNSTR LOGIC T EX A S I N S T R { L O G I C ! 1 1 91D 74690 D T-5£-0? D E | 0 ^ 1 7 2 3 DD74h1G 5 1 ~ SN 74 A S 18 2 3 9-BIT BUS INTER FA CE FLIP-FLUPS WITH 3-STATE OUTPUTS APRIL 1 9 8 7 NT PACKAGE Center V q c ar|d GND Configuration Provides Minimum Lead Inductance in High

sc filter ic mf10

Abstract: TLC20CN MF10C xq200
Contextual Info: TLC10/MF10A, TLC20/MF1 OC UNIVERSAL DUAL SWITCHED CAPACITOR FILTER D2952, AUGUST 1 9 8 6 -R E V IS E D NOVEMBER 1988 Maximum Clock to Center-Frequency Ratio Error TLC10 . . i ± 0.6% TLC20 . . . ± 1.5% N DUAL-IN-LINE PA CKAG E TO P VIEW I 1LP □ 1 L J 2 0 ] 2 L P