CASEY Search Results

50000003

Abstract: KEMET C0603C104K5RAC BERG jumper manual counter on breadboard AND8020 C0603C104K5RAC NBLVEP16VR NBLVEP16VREVB T491D226K016AS
Contextual Info: NBLVEP16VREVB NBLVEP16VR Evaluation Board Prepared by: Casey Stys http://onsemi.com EVALUATION BOARD MANUAL Board Features DESCRIPTION • Accommodates the Electrical Characterization for the The NBLVEP16VR is an ECL differential Receiver/ Driver with Oscillator Gain Stage. The NBLVEP16VR

Contextual Info: QFN16EVB Evaluation Board Manual for High Frequency QFN-16 Prepared by: Casey Stys ON Semiconductor http://onsemi.com EVALUATION BOARD MANUAL Introduction datasheet located at www.onsemi.com. The datasheet contains the technical device specifications. ON Semiconductor has developed the QFN16EVB

MC100EP33

Abstract: AND8040 MC100EP1 NB4N507 casey
Contextual Info: AND8248/D System Clock Generators: A Comparison of a PLL Synthesizer vs. a Crystal Oscillator Clock Prepared by: Casey Stys and Paul Shockman ON Semiconductor Application Engineers http://onsemi.com APPLICATION NOTE Abstract An electronic system requires a reliable, precision timing

Quartz Clock crystal

Abstract: 4 MHz Crystal Oscillator crystal oscillator datasheets Three phase oscillator AND8040 MC100EP11 MC100LVEP34 oscillator MHz Crystal divider oscillator canned quartz 20 MHZ
Contextual Info: AND8248/D System Clock Generators: A Comparison of a PLL Synthesizer vs. a Crystal Oscillator Clock Prepared by: Casey Stys and Paul Shockman ON Semiconductor Application Engineers http://onsemi.com APPLICATION NOTE Abstract An electronic system requires a reliable, precision timing

TTC-272F

Abstract: CSA-C22 TAMURA TTC
Contextual Info: REV. Status ISSUE 1 10/27/94 TS P R E P A R E D BY: K. B re n n a n EN G IN EER: T. S h io za w a APPROVED: V- Casey A. Electrical Specifications 25" C 1. Pri Source Impedance; 600 0 2. Sec Load Impedance; 600 0 3. Operating Level; —45 dBm to + 7 dBm and 0mA DC

ASTM-D-4565

Abstract: lexan 3412 zytel fr 10 fr52g30l C17410 C1741 zytel HTN meta gig BUS-19-002 BUS-03-601
Contextual Info: PRODUCT SPECIFICATION MetaGig I/O Connector System Preliminary GES-12-022 1 D. Casey 1.0 18 2 07/09/98 OBJECTIVE This specification defines the performance, test, quality and reliability requirements of the MetaGig connector system receptacle/plug and receptacle/cable assembly .

SPARTAN-3e microblaze

Abstract: Intel StrataFlash Parallel NOR Flash PROM rs232 parallel flash programmer picoblaze Intel StrataFlash Parallel NOR Flash PROM for spartan3e xilinx spartan-3E FPGA Image Load UG257 fpga spartan 2 intel FPGA SP3E1600E
Contextual Info: Application Note: Embedded Processing Using and Creating Flash Files for the MicroBlaze Development Kit - Spartan-3E Edition R XAPP963 v1.1 November 28, 2007 Author: Casey Cain, Sundararajan Ananthakrishnan Abstract This application note describes the files for programming the StrataFlash memory for the

D103D

Abstract: Q 101 Q102 TRANSISTOR d106d D104d C101B input output npn 547 transistor cc11b d108d AND8157/D D105u
Contextual Info: AND8157/D ECLinPS MAX] SiGe SPICE Modeling Kit Prepared by: Casey Stys and Paul Shockman http://onsemi.com APPLICATION NOTE Objective Table 1. Schematics and Netlist Nomenclature The objective of this kit is to provide sufficient circuit schematic and SPICE parameter information to perform

SPST momentary push button

Abstract: crystal 16.000 76STC04 67-1046-ND AND8020 NBC12429 NBC12430 NBC12439 Crystal 16.000 MHz 12439
Contextual Info: NBC124XXEVB/D NBC12429/12430/12439 Evaluation Board Prepared by: Casey Stys http://onsemi.com EVALUATION BOARD MANUAL Device Description The NBC12429/430/439 Evaluation Board is equipped with a PLCC−28 surface mount socket. The NBC124XX−series are high−speed, programmable

AP-606

Abstract: PCMCIA 1.0 28F0016SA MC020FLSP 292096
Contextual Info: intei AP-606 APPLICATION NOTE Interchangeability of Series 1, Series 2, and Series 2 + Flash Memory Cards SEAN CASEY TECHNICAL MARKETING ENGINEER November 1994 _ IF ^ iL D IM lO K lÄ l^ ir 6-170 I Order Number: 292158-001 INTERCHANGEABILITY OF SERIES 1, SERIES 2, AND

pcmcia flash card

Abstract: AP-606 Intel AP-606 iMC020FLSP iMC001FLKA iMC002FLKA integrated circuit array interface electrical 28F008SA 28F010 28F016SA
Contextual Info: E AP-606 APPLICATION NOTE Interchangeability of Series 1, Series 2 and Series 2+ Flash Memory Cards SEAN CASEY TECHNICAL MARKETING ENGINEER September 1994 Order Number: 292158-001 Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever,

X912

Abstract: microblaze SP305 XAPP912 Xilinx Parallel Cable IV spartan-3
Contextual Info: Application Note: Embedded Processing R XAPP912 v1.3 June 1, 2007 Abstract Reference System: MCH OPB DDR SDRAM with OPB Central DMA Author: Casey Cain This application note describes a reference system that demonstrates the use of the MultiCHannel (MCH) On-chip Peripheral Bus (OPB) Double Data Rate (DDR) Synchronous DRAM

AM0393-320R

Abstract: IPC-A-600E MIL-P-55110D MIL-P-55110-D PCB BOARD DIMENSION BY SMA CONNECT AN8020 casey C0603C104K4RAC HP6624A marking code C3 SMD ic
Contextual Info: XOCLCC6EVB Crystal Clock Oscillator Module Evaluation Board Manual for NBX Family in 6 Pin CLCC 5mm X 7mm Package http://onsemi.com Generic Evaluation Board: XOCLCC6EVB Devices: NBXxxxx Prepared by: Senad Lomigora, Casey Stys and Paul Shockman Description

EM80 MIC

Abstract: ep13-t38 em80 EM80-PM12 lm747 application design of 20 khz step up ferrite transformer PMT3(310)-350-04-SN PRIMO em80 em80 tube PMT3(310)-250-14-SN
Contextual Info: National Semiconductor Application Note 509 Casey Tsai and Bart Vos October 1989 INTRODUCTION The TP3401 Digital Adapter for Subscriber Loops DASL is a low-cost burst-mode transceiver for 144 kb s full-duplex on single twisted-pair PBX and private network loops up to

D103D

Abstract: D104D d106d D108D C101B Q102 R101 R105 R107 BF179
Contextual Info: AND8157/D ECLinPS MAX] SiGe SPICE Modeling Kit Prepared by: Casey Stys and Paul Shockman http://onsemi.com APPLICATION NOTE Objective Table 1. Schematics and Netlist Nomenclature The objective of this kit is to provide sufficient circuit schematic and SPICE parameter information to perform

intel batch MARKING flash

Abstract: spi flash spartan 6 intel batch MARKING date code marking intel strataflash intel nor flash Intel StrataFlash Parallel NOR Flash PROM XAPP1106 flash memory application image processing using xilinx platform studio SPARTAN-3A DSP 1800A
Contextual Info: Application Note: Embedded Processing R XAPP1106 v1.2 January 27, 2009 Using and Creating Flash Files for the MicroBlaze Development Kit - Spartan3A DSP 1800A Starter Platform Author: Sundararajan Ananthakrishnan/Casey Cain Abstract This application note describes the files for programming the serial Flash memory and the

Contextual Info: VISHAY DALE www.vishay.com Networks / Arrays Application Note Understanding Dual Terminator Resistor Networks By Mike Casey One of the least understood resistor network schematics in the industry today is the dual-resistor terminator schematic shown below in the 8-pin SIP and in the 16-pin DIP configuration.

Intel StrataFlash Parallel NOR Flash PROM

Abstract: SPARTAN-3e microblaze XILINX/SPARTAN 3E STARTER BOARD sp3e1600e SPARTAN 3E STARTER BOARD spi flash programmer XAPP978 XAPP445 ddr spi flash XILINX/intel nor flash
Contextual Info: Application Note: Embedded Processing R XAPP978 v1.1 June 4, 2007 Abstract FPGA Configuration from Flash PROMs on the Spartan-3E 1600E Board Author: Casey Cain This application note describes three FPGA configuration modes using Flash PROMs. These modes are BPI Up mode, BPI Down mode, and SPI mode. The step-by-step process to

PCMCIA pinout

Abstract: Value Series 100 flash memory pcmcia flash card register status 28F008SA 28F016SA intel DOC Signal Path Designer
Contextual Info: E AP-622 APPLICATION NOTE Upgrade to the Value Series 100 Flash Memory Card SEAN CASEY TECHNICAL MARKETING ENGINEER October 1995 Order Number: 292177-001 Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including

Bluetooth flow chart

Abstract: Cypress Semiconductor USB
Contextual Info: Overcoming UTMI Interface Limitations in USB-Enabled Handsets Triton Hurd, Sr. Applications Engineer at Cypress Semiconductor Ray Casey, Product Marketing Manager at Cypress Semiconductor USB has quickly become widespread as the interface of choice for mobile

SPARTAN 3E STARTER BOARD

Abstract: Intel StrataFlash Parallel NOR Flash PROM SPARTAN-3e microblaze rs232 parallel flash programmer XAPP978 SP3E1600E spi flash programmer XILINX/SPARTAN 3E STARTER BOARD XAPP951 SPARTAN 3e 1600e
Contextual Info: Application Note: Embedded Processing FPGA Configuration from Flash PROMs on the Spartan-3E 1600E Board XAPP978 v1.2 November 5, 2010 Abstract Author: Casey Cain This application note describes three FPGA configuration modes using Flash PROMs. These modes are BPI Up mode, BPI Down mode, and SPI mode. The step-by-step process to

str f 6456

Abstract: str x 6456 SM 5126 BP STR F 6168 str 6668 STR G 6352 STR 6456 str f 6468 321 CJ 7121 AXP 209 IC
Contextual Info: Tem ic Se ni i co n fi li c t ci Sales Offices rs Addresses Europe France TE M IC France Les Q uadrants 3. avenue du centre B.P. 309 78054 S t.-Q uentin-en-Y veL nes Cedex Tel: 33 I 3060 7000 F a x :33 I 3060 V 11 i Germany TE M IC TE LEFU N K EN m icroelectronic G m bH

BV EI 304 3160

Abstract: str f 6456 ic sw 2604 BV EI 304 3510 BV EI 303 3535 STR 6755 STR 6456 STR G 6352 AMI Semiconductor 9449 sw 2604 ic
Contextual Info: T e m ic Sales Offices Semiconductors Addresses Europe France TEMIC France Les Quadrants 3, avenue du centre B.P. 309 78054 St.-Q uentin-en-Y velines Cedex Tel: 33 1 3060 7000 Fax: 33 1 3060 7111 Germany TEMIC TELEFUNKEN m icroelectronic GmbH Erfurter Strasse 31

Contextual Info: C h a p te r 6 CPU Exception Processing Notes Introduction This chapter describes the CPU exception processing, discusses the format and use of each CPU exception register and concludes with a description of each exception's cause as well as CPU service procedures. For information about Floating-Point Unit exceptions, refer to Chapter 7.