CASCADING Search Results

sn74f160

Abstract: SN54F160
Contextual Info: SN 54F160A, SN 54F162A, SN 74F160A, SN 74F162A SYNCHRONOUS 4-BIT DECADE COUNTERS D2932, MARCH 1987-REVISED JANUARY 1989 • Internal Look-Ahead for Fast Counting • Carry O utput fo r n-Bit Cascading • Fully Synchronous Operation for Counting • Package Options Include Plastic "Sm all

Contextual Info: SN74F161A SYNCHRONOUS 4-BIT BINARY COUNTER SDFS056A - D2932, MARCH 19B7-REVISED OCTOBER 1993 • Internal Look-Ahead Circuitry for Fast Counting • Carry Output for N-Bit Cascading D OR N PACKAGE TOP VIEW • Fully Synchronous Operation for Counting • Package Options Include Plastic

Contextual Info: UT54ACS 139/UT54ACTS 139 Radiation-Hardened Dual 2-Line to 4-Line Decoders/Demultiplexers PINOUTS FEATURES 16-Pin DIP Top View • Incorporates two enable inputs to simplify cascading and/or data reception • 1.2 1 radiation-hardened CMOS - Latchup immune

74278

Contextual Info: TYPES SN54278, SN74278 4-BIT CASCADABLE PRIORITY REGISTERS M AY 1 972 —R E V ISE D A P R IL 1 98 5 Latched Data Inputs Serve as Buffer Register and Can also: Synchronize Data Acquisition "Debounce" Mechanical Switch Input • Cascading Input PO and Output P1

SDFS089

Contextual Info: SN74F169 SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER SDFS089 - MARCH 1987 - REVISED OCTOBER 1393 Fully Synchronous Operation for Counting and Programming d or n package <TOP v i e w Internal Look-Ahead Circuitry for Fast Counting U /D [ 1 C LK [ 2 Carry Output for N-Bit Cascading

D3318

Contextual Info: 74AC11139 DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER D3318, JULY 1989 - R EV ISED APRIL 1993 * Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems * Incorporates Two Enable Inputs to Simplify Cascading and/or Data Reception

Contextual Info: UT54ACS 169/UT54ACTS 169 Radiation-Hardened 4-Bit Up-Down Binary Counters FEATURES • • • • • • • • • • Fully synchronous operation for counting and programming Internal look-ahead for fast counting Carry output for n-bit cascading Fully independent clock circuit

ic 4017 pin configuration

Abstract: pin diagram of IC 4017 n ic 4017 PIN DIAGRAM IC 4017 B operation of 4017 ic ic 4017 tl 4017 4017 counter IC 4017 DC 4017 IC
Contextual Info: SN 54H C4017, SN74HC4017 DECADE COUNTERS/DIVIDERS D 2 6 8 4 . DECEMBER 1 9 8 2 -R E V IS E D JUNE 1 9 8 9 Carry-Out Output for Cascading S N 5 4 H C 4 0 1 7 . . . J P AC KA G E S N 74H C 4017 N P AC KAG E Divide-by-N Counting ITO P V IE W DC Clock Input Circuit Allows Slow Rise

SN54F161

Contextual Info: SN54F161 A, SN54F163A, SN74F161 A, SN74F163A SYNCHRONOUS 4-BIT BINARY COUNTERS D 2 9 3 2 , M A R CH 1 9 8 7 - R E V IS E D JA N U A R Y 1 98 9 • Internal Look-Ahead for Fast Counting • Carry Output for n-Bit Cascading • Fully Synchronous Operation for Counting

Contextual Info: UT54ACS 169/UT54ACTS 169 Radiation-Hardened 4-Bit Up-Down Binary Counters FEATURES PIN O U T S • Fully synchronous o p eratio n for counting and pro­ gram m ing • Internal look-ahead for fast counting • Carry output for n-bit cascading • Fully independent clock circuit

SN74F138

Contextual Info: SN54F138, SN74F138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDFS051 A - D2932, MARCH 1987 - REVISED OCTOBER 1993 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception

SN54ALS137

Contextual Info: SN74ALS137, SN74AS137, SN54ALS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES D2661, APRIL 1982 - REVISED MAY 1986 Combines Decoder and 3-Bit Address Latch Incorporates 2 Output Enables to Simplify Cascading SN54ALS137 . . . J PACKAGE SN74ALS137, SN74AS137 . . . D OR N PACKAGE

HA139

Contextual Info: SN54AHC139, SN74AHC139 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCLS259K − DECEMBER 1995 − REVISED MARCH 2003 D Memory Decoders and Data-Transmission Systems Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception SN54AHC139 . . . J OR W PACKAGE

Contextual Info: CD54AC163, CD74AC163 4-BIT SYNCHRONOUS BINARY COUNTERS SCHS299B – APRIL 2000 – REVISED MARCH 2003 D D D D CD54AC163 . . . F PACKAGE CD74AC163 . . . E OR M PACKAGE TOP VIEW Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting

TPIC6A596

Abstract: TPIC6A596DW TPIC6A596DWG4 TPIC6A596DWR TPIC6A596DWRG4 TPIC6A596NE
Contextual Info: TPIC6A596 POWER LOGIC 8ĆBIT SHIFT REGISTER SLIS094A − MARCH 2000 − REVISED MAY 2005 D D D D D D D D Low rDS on . . . 1 Ω Typ Output Short-Circuit Protection Avalanche Energy . . . 75 mJ Eight 350-mA DMOS Outputs 50-V Switching Capability Enhanced Cascading for Multiple Stages

CD4585BMS

Abstract: IOH15
Contextual Info: CD4585BMS CMOS 4-Bit Magnitude Comparator December 1992 Features Pinout • High Voltage Type 20V Rating CD4585BMS TOP VIEW • Expansion to 8, 12, 16 . . .4N Bits by Cascading Units B2 1 16 VDD A2 2 15 A3 (A = B)OUT 3 14 B3 (A > B)IN 4 13 (A > B)OUT (A < B)IN

14KA

Abstract: CD4094BMS IOH15 LA 71091 D 71086
Contextual Info: CD4094BMS CMOS 8-Stage Shift-and-Store Bus Register December 1992 Features Pinout • High Voltage Type 20V Rating CD4094BMS TOP VIEW • 3-State Parallel Outputs for Connection to Common Bus • Separate Serial Outputs Synchronous to Both Positive and Negative Clock Edges for Cascading

40193

Abstract: HCF401XXBEY 40192B 40193B HCC40192B HCC40193B HCC401XXBF HCF40192B HCF401XXBC1
Contextual Info: HCC/HCF40192B HCC/HCF40193B PRESETTABLE UP/DOWN COUNTERS DUAL CLOCK WITH RESET 40192B – BCD TYPE 40193B – BINARY TYPE . . . . . . . INDIVIDUAL CLOCK LINES FOR COUNTING UP OR COUNTING DOWN SYNCHRONOUS HIGH-SPEED CARRY AND BORROW PROPAGATION DELAYS FOR CASCADING

pin diagram priority encoder 74148

Abstract: priority encoder 16 to 4 74148 74148 PIN DIAGRAM pin diagram of 74148 priority encoder 74148 74148 pin diagram and function table 74148 74148 pin configuration pin diagram encoder 74148 encoder 74148
Contextual Info: 74148 Signetìcs Encoder 8-Input Priority Encoder Product Specification Logic Products FEATURES • • • • • • • • Code conversions Multi-channel D/A converter Decimal-to-BCD converter Cascading for priority encoding of "N" bits Input Enable capability

Contextual Info: SN54F138, SN74F138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDFS051B – MARCH 1987 – REVISED JULY 1996 D D D Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception

4AC17

Abstract: texas instruments fifo cascaded SN74ACT7808
Contextual Info: SN74ACT7808 2048 x 9 STROBED FIRST-IN, FIRST-OUT MEMORY _SCAS205B - FEBRUARY 1991 - REVISED SEPTEMBER 1995 Load Clocks and Unload Clocks Can Be Asynchronous or Coincident * 2048 Words by 9 Bits • Expansion Logic for Depth Cascading 9 Empty, Full, and Half-Full Flags

"Parity Checker generator odd-even

Abstract: LS180 LS280 T54LS280D2
Contextual Info: T54LS280 T74LS280 9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS DESCRIPTION The T54LS280/T74LS280 is a universal 9-Bit OddEven Parity Generator/Checker. It is composed of odd/even outputs to facilitate either odd or even parity. By cascading, the word length can be easi­

CTR DIV 8

Abstract: CTR DIV 6 counter Y6 11
Contextual Info: C:>‘i y HIGHSPEED CMOS LOGIC - / TYPES SN54HC4022, SN74HC4022 OCTAL COUNTERS/DIVIDERS □ 2 83 1. MARCH 1984 S N 5 4 H C 4 0 2 2 . . . J PACKAGE SN 74H C 4022 J OR N PACKAGE Carry-Out Output for Cascading Divlde-by-N Counting ITO P V IE W DC Clock Input Circuit Allows Slow Rise

Contextual Info: CD54AC161, CD74AC161 4-BIT SYNCHRONOUS BINARY COUNTERS SCHS239C – SEPTEMBER 1998 – REVISED MARCH 2003 D D D D D D CD54AC161 . . . F PACKAGE CD74AC161 . . . E OR M PACKAGE TOP VIEW Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading