CA5B Search Results

TMS34061FNL

Abstract: lad1-5v TMS34070NL S3406 TL 413 SPVU001 MJ340 TA2625
Contextual Info: SM J 3 4 0 1 0 GRAPHICS SYSTEM PROCESSOR NOVEMBER 1 98 8 - • Military Temperature . . . - 5 5 ° C to 12 5°C • Instruction Cycle Time: 200 ns . . . S M J3 4010-40 160 ns . . . S M J3 4010-50 REVISED SEPTEMBER 1989 GB PACKAGE 68-PIN GRID ARRAY TOP VIEW

s - ck5t

Abstract: CA52
Contextual Info: Preliminary KMM5321200BW/BWG DRAM MODULE KMM5321200BW/BWG Fast Page Mode 1Mx32 DRAM SIM M , 1K Refresh, 5V, using 1Mx16 DRAM GENERAL DESCRIPTION FEATURES The Samsung KMM5321200BW is a 1M bit x 32 Dynam ic RAM high density m em ory module. The • Part Identification

Contextual Info: «HYUNDAI H Y 5 1 1 7 1 O O A S e r ie s 1 6 M x 1 - b it CM O S DRAM DESCRIPTION The HY5117100A is the new generation and fast dynamic RAM organized 16,777,216 x 1-bit. The HY5117100A utilizes Hyundai's CMOS silicon gate process technology as well as advanced circuit techniques to provide wide

Contextual Info: •HY U ND A I HYM572A414A F-Series Unbuffered 4M x 72-bit CMOS DRAM MODULE _ with EXTENDED DATA OUT DESCRIPTION T ie HYM572A414A is a 4M x 72-bit EDO mode CMOS DRAM module consisting of eighteen HY5117804B in 28/28 SOJ or TSOP-II and one 2048 bit EEPROM on a 168 pin glass-epoxy printed circuit board. 0.1nF and 0.01 ^F

Contextual Info: ^HYUNDAI HYM564224A R-Series Unbuffered 2M x 64-bit CMOS DRAM MODULE _ with EXTENDED DATA OUT DESCRIPTION The HYM564224A is a 2M x 64-bit EDO mode CMOS DRAM module consisting of eight HY5118164B in 42/42 pin SOJ or 44/50 pin TSOP-II and one 2048 bit EEPROM on a 168 pin glass-epoxy printed circuit board. 0.1 ¡aF and

KM44C4104bk

Abstract: cd-rom circuit diagram
Contextual Info: K M 4 4 C 4 10 4 B K CMOS D R A M ELECTRONICS 4M x 4 Bit CMOS Dynamic RAM with Extended Data Out DESCRIPTION This is a family of 4,194,304 x 4 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row, so called Hyper Page Mode. Power

Contextual Info: - PRELIMINARY - February 1996 Edition 1.0 FUJITSU P R O D U C T PR O F IL E S H E E T MB81V4405C-60/-70 CMOS 1 M X 4 BIT HYPER PAGE MODE DRAM CMOS 1,048,576 x 4 bit Hyper Page Mode Dynamic RAM The Fujitsu MB81V4405C is a fully decoded CMOS Dynamic RAM DRAM that contains 4,194,304

A13B1

Contextual Info: 1 1234455678 96ABCADEFCC1C3C66C 1 131C7BA1C C C C C C C 13C9A1C 1 CDE33AAF1116511C11551 !61"F#$11#%71 1 #&11&11C12&6!'&1 ' !1!155(1&&11 !51 !61'51!*11)!571#&51C1! 137E+,11(151'51 1

Contextual Info: FUJITSU MICROELECTRONICS 7Û 3749762 FUJITSU MICROELECTRONICS D e | 374c17t,a 0003Gb3 □ |' 78C 03063 FUJITSU M OS M em ories • MB85204-10, MB85204-12, MB85204-15 262,144 x 4-Bit Dynamic Random Access Memory SIP Module Description The Fujitsu MB85204 is a fully decoded, 262,144 word X 4-bit

Contextual Info: 1 1234456789 1 ABCDEF18DD1DF7CD3FD77D 1 1D31FD811 1 1 1 1 1 1DFF3DA11 CD51 EF3381 1 1 1 51 561 1  !1 " CD1 !1 D1 1 ,E1 2%D6-#D1 -&%1 %1 55&%1 D#D1

Contextual Info: |U |IC=RO N 2 MEG DRAM MODULE X MT18D236 36 DRAM MODULE 2 MEG x 36 DRAM FAST PAGE MODE FEATURES • Common RAS control per side pinout in a 72-pin single-in-line package • High-performance, CMOS silicon-gate process. • Single 5V ±10% power supply • All device pins are fully TTL compatible

Contextual Info: MICRON TECHNOLOGY INC SSE D • b 1 1 1 5 4 =5 O O O S l b ? TE7 ■ MRN MT24D88C240 2 MEG x 40, 4 MEG x 20 1C DRAM CARD 1C DRAM CARD 8 MEGABYTES 2 MEG x 40, 4 MEG x 20 PIN ASSIGNMENT End View 88-Pin Card (U-1) • JEIDA, JEDEC and PCMCIA standard 88-pin IC

Contextual Info: M I CR ON T E C H N O L O G Y INC 5SE ]> bl 1 1 S 4 e} OQOMfcjfl? 332 MICRON • 4 MEG TtCHNOLOGV INC DRAM MODULE X 8 IURN MT8D48 DRAM MODULE 4 MEG X 8 DRAM FAST PAGE MODE MT8D48 LOW POWER, EXTENDED REFRESH (MT8D48 L) FEATURES • Industry standard pinout in a 30-pin single-in-line

Contextual Info: MT4C4004J 1 MEG X 4 DRAM M IC R O N DRAM 1 MEG x 4 DRAM FEATURES _ • Four independent CAS controls, allowing individual manipulation to each of the four data Input/Output ports DQ1 through DQ4 . • Offers a single chip solution to byte level parity for 36bit words when using 1 Meg x 4 DRAMs for memory

Contextual Info: M IC R O N □ P A M _ _ _ _ . . . 512K MT16D51232 32. 1 MEG x 16 DRAM MODULE X 5 1 2 K _ x 3 2 > 1 M E G x 16 FAST PAGE MODE (MT16D51232 LOW POWER, EXTENDED REFRESH (MT16D51232 L) MODULE IV IV /U U I.L . FEATURES PIN ASSIGNMENT (Top View) OPTIONS 72-Pin SIMM

Contextual Info: MT10D25640 256K X 40 DRAM MODULE |U |IC = R O N 256K x 40 DRAM FAST PAGE MODE MT10D25640 LOW POWER, EXTENDED REFRESH (MT10D25640 L) FEATURES • • • • • • • • • PIN ASSIGNMENT (Top View) 72-pin single-in-line package High-performance, CMOS silicon-gate process.

Contextual Info: M IC R O N MT8C8024 DRAM MODULE 1MEG x 8 DRAM FAST PAGE MODE PIN ASSIGNMENT (Top View OPTIONS Vcc CÄ5 DQ1 A0 A1 DQ2 A2 A3 Vss DQ3 A4 A5 DQ4 A6 A7 DQ5 A8 A9 NC DQ6 W Vss DQ7 NC DQ8 NC raS NC NC Vcc MARKING • Tim ing 80ns access 100ns access 120ns access

Contextual Info: ADVANCE MT4 L C1M16CX S 1 MEG X 16 DRAM IURN blllSHT I3004b21 4HT p ilC R O N MICRON TECHNOLOGY INC SSE » DRAM X 1 6 D R A M m 1 M E G 5.0V SELF REFRESH (MT4C1M16CX S) 3.0/3.3V, SELF REFRESH (MT4LC1M16CX S) FEATURES PIN ASSIGNMENT (Top View) • Self Refresh, ie "Sleep Mode"

Contextual Info: MICRON 256K DRAM MT4C4258 X 4 DRAM 256K X 4 DRAM DRAM STATIC COLUMN FEATURES • Industry standard x4 pinout, timing, functions and packages • High-performance, CMOS silicon-gate process • Single +5V +10% power supply • Low power, 3mW standby; 175mW active, typical

Contextual Info: M IC R O N 512K 512K X MT20D51240 40 DRAM MODULE 40 DRAM FAST PAGE MODE MT20D51240 LOW POWER, EXTENDED REFRESH (MT20D51240 L) FEATURES • • • • • • • • • PIN ASSIGNMENT (Top View) 72-pin single-in-line package High-performance, CMOS silicon-gate process.

Contextual Info: blllSM'ì 0004371 2E2 B U R N SSE D MICRON TECHNOLOGY INC ADVANCE ic n o N MT4C8512/3 5 1 2 K x 8 DRAM DRAM 512K x 8 DRAM FAST PAGE M O D E • Industry standard x8 pinouts, timing, functions and packages • Address entry: 10 row addresses, nine column addresses

Contextual Info: KM44V16000AS CMOS D R AM ELECTRONICS 1 6 M x 4 B i t CMOS Dynamic RAM with Fast Page Mode DESCRIPTION This is a family of 16,777,216 x 4 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Refresh cyde 4K Ref. or 8K Ref. , access time(-5, -6,

KM44C4100BK

Contextual Info: KM4 4 C 4 1 OOB K CMOS D R AM ELECTRONICS 4 M X 4 Bit C M O S Dynamic H A M with Fast Page M ode DESCRIPTION This is a family of 4,194,304 x 4 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Power supply voltage +5.0V or +3.3V , refresh cycle

Contextual Info: KM44V41OOA/AL/ALL/ASL CMOS DRAM 4M x 4 Bit CMOS Dynamic RAM with Fast Page Mode FEATURES GENERAL DESCRIPTION T h e S a m s u n g K M 4 4V 41 O O A /A L /A L L /A S L is a h ig h s p e e d C M O S 4 ,1 9 4 ,3 0 4 b i t x 4 D y n a m ic R a n d o m • Performance range: