BSDL Search Results

M9703

Abstract: HP3070
Contextual Info: BSDL SOURCE CODE - PMC_Sierra_Cells for PMC - Sierra revision : VHDL Package and Package Body 1.0 created by : James Lamond Hewlett Packard Canada Ltd date : 20 December 1995 package PMC_Sierra_Cells is use STD_1149_1_1990.all; constant cele0 : CELL_INFO;

drca

Abstract: vhdl code for a 16*2 lcd HP3070 PM7346 SBGA256 G4 BC 30 B0278
Contextual Info: BSDL SOURCE CODE - PMC_Sierra_Cells for PMC - Sierra revision : VHDL Package and Package Body 1.0 created by : James Lamond Hewlett Packard Canada Ltd date : 20 December 1995 package PMC_Sierra_Cells is use STD_1149_1_1990.all; constant cele0 : CELL_INFO;

DM74ALS

Abstract: DM74ALS22BM DM74ALS22BN M14A N14A
Contextual Info: T 22B NATIONAL SEMICOND -CLOGICJ bSDliaS OGbilSl 1 31E D r '^ - z d - ò ò National Semiconductor DM74ALS22B Dual 4-Input NAND Gate with Open Collector Outputs General Description Features This device contains two independent gates, each of which performs the logic NAND function. The open-collector out­

Xilinx jtag cable hardware user guide

Abstract: ieee 1532 PAD123 BSDL P103 P104 P105 P112 P206 PQ208
Contextual Info: Application Note: Spartan-3 FPGA Series R Using BSDL Files for Spartan-3 Generation FPGAs XAPP476 v1.1 June 19, 2005 Summary BSDL (Boundary Scan Description Language) files are provided for every part and package combination of IEEE 1149.1 (JTAG) compatible devices produced by Xilinx, including all the

KIB 28

Abstract: 54H71DM 54H71FM 74H71DC 74H71FC 74H71PC
Contextual Info: NA TI ON A L {LOGIC} SE MICOND ÜEE D | bSDli eS .□□fc.37Dfl 5 | 71 CO N N ECTIO N DIAGRAM S PINOUT A 54H/74H71 JK MASTER/SLAVE FLIP-FLOP With A N D -O R Inputs D E S C R IP T IO N — The '71 is a high speed J K master/slave flip-flop with AND-OR gate inputs. The AND-OR gate inputs for entry into the master sec­

VME64

Abstract: VME backplane pinout
Contextual Info: bSDllSS 007^025 7S2 • NSC1 PRELIMINARY 16245 National ÆM Semiconductor 54/74ETL16245 16-Bit Data Transceiver with Incident Wave Switching Improved TTL-compatible input threshold range High drive TTL-compatible outputs I o h = “ 60 mA, I q l = 90 mA

tl 2262 am

Abstract: TL 2272 R DIODE Ch6h TL 2262 2272 t4 tl 2262 am data ADC0646 ADC0844 ADC0848 NSL5027
Contextual Info: ADC0844/ADC0848 NATL SEMICOND LINEAR 5ÖE D • bSDllSM G 0 7 3 cìScì 3D7 « N S C S S3 National i-si-io-ce mm Semiconductor ADC0844/ADC0848 8-Bit juP Compatible A/D Converters with Multiplexer Options General Description Features The ADC0844 and ADC0848 are CMOS 8-bit successive

format .pof

Abstract: vhdl code for All Digital PLL led matrix vhdl code GAL Gate Array Logic OCR library ALTERA APU EPLD JEDEC MAPPING IR LED array application of programmable array logic
Contextual Info: Abbreviations January 1998 The 1998 Data Book uses the following abbreviations and acronyms: ACAP ACCESS AHDL AMPP APD APU AN AS ASCII ASIC ASSP ATM BGA BNF BPR BSC BSDL BST CAE CerDIP CMD CMOS CPLD CPU CQFP CRC DIP DRAM DS DSP DUT EAB EAU EDA EDF EDIF

M68040

Abstract: MC68EC040 MC68LC040 BB 36 931 937 motorola
Contextual Info: INDEX -A - Bus Cycle, 7-29, 7-35, 9-20 BSDL Description, 6-15 Access Control Unit, 1-2, B-4, B-5 Buffer Selection, 7-69 Access Control Unit Register, B-5; Burst Mode Operations, 4-3, 4-11, 5-9 Field Definitions, B -6-B -7 Burst Bus Cycles, s e e Bus Cycles

T431

Abstract: DS21Q352 DS21Q354 DS21Q55 DS21Q552 DS21Q554 SCT3
Contextual Info: Maxim > App Notes > TELECOM Keywords: BSDL, JTAG, scan chain, boundary scan, chain mapping Jun 06, 2003 APPLICATION NOTE 406 DS21Qx5y BSDL Scan Chain Mapping Abstract: This application note describes the JTAG hardware boundary scan functions of the quad port single

DS8640J

Abstract: DS8640 DS8640N
Contextual Info: DS7640/DS8640 NATL S E N K E N D {MEMORY} IG E D | bSDllSb T | 7 £TX- 3-0 3 National Semiconductor - ¿ DS7640/DS8640 Quad NOR Unified Bus Receiver General Description Features The DS7640 and DS8640 are quad 2-input receivers de­ signed for use in bus organized data transmission systems

ALS20A

Contextual Info: î 1020A NATIONAL SEMICOND -CLOGICD- 31E D bSdllSa OOtTBTl T National Semiconductor DM74ÂLS1020A Dual 4-Input NAND Buffer General Description Features These devices contain two independent 4-input buffers, each of which performs the logic NAND function. The

Contextual Info: NATIONAL SEniCON» -CLOGIO bSDllEa OQbTSSb H B1E D IO <0 ADVANCE INFORMATION National Semiconductor <o l'*/û>~09-03 DM74ALS299 TRI-STATE 8-Bit Universal Shift/Storage Register Description Features This eight-bit universal register features multiplexed inputs/

74174PC

Abstract: 74174
Contextual Info: NATIONAL SEMICOND -ELOGIO OPE D | bSDllSB üüb3öfl4 3 | 174 T -4 6 -0 7 -1 0 CO NNECTIO N DIAGRAM PINOUT A 54/74174 54S /74S 174 54LS /74LS 174 1 HEX D FLIP-FLOP DESCRIPTION — The '174 is a high speed hex D flip -flo p. The device is used prim arily as a 6-bit edge-triggered storage register. The inform ation

MM74HC574

Contextual Info: NATIONAL SEflICOND -CLOGIO IDE D | bSDllBg DQfc,5M37 □ | 3 pga National Ælm Semiconductor -r-fc ,-o i,~ u MM54HC574/MM74HC574 TRI-STATE Octal D-Type Edge-Trîggered Flip-Flop General Description The 54HC/74HC logic family is speed, function, and pinout

Contextual Info: NATIONAL SENICOND -CLOGIC} IDE D | bSDliaS T - 5 7 0 | - / / MM54HC4316/MM74HC4316 Quad Analog Switch with Level Translator General Description Features These devices are digitally controlled analog switches im­ plemented in advanced silicon-gate CMOS technology.

LM555

Abstract: LM55SCN LM555CH RETS555X LM555J LM555CJ monostable adjustable one-shot pulse application LM555 as a monostable multivibrator LM555H lm555 application
Contextual Info: LM555/LM555C S6E D • bSDllSM D077flbfl DTfi H N S C E S3 National m J k NATL SEni<:0N]> linear Semiconductor 'f 'S I \H LM555/LM555C Timer General Description The LM555 is a highly stable device for generating accurate time delays or oscillation. Additional terminals are provided

IC 74122

Abstract: cx - 032 LS 74122 74122PC 4165F
Contextual Info: NATIONAL SÈ H ICÔN» {LOGIC} 0 2 E D | bSDllEE DObB?^? fi | T 'S /'/r 1 2 2 CONNECTION DIAGRAM PINOUT A 54/74122 R E T R IG G ERABLE RESETTABLE MULTIVIBRATOR DESCRIPTION — The '122 features positive and negative dc level triggering inputs, complementary outputs, an optional 10 kft internal timing resistor

A-254168-2

Abstract: VOLTAGE REGULATOR IC LM SERIES lm 2490 VR9F Arnold A-254168-2 core with 60 turns LM336H-2.5 LM136-2.5
Contextual Info: SñE J> bSDllEH DD7441Ô 177 « N S C 2 National oí Semiconductor LM136-2.5/LM236-2.5/LM336-2.5V Reference Diode General Description The LM136-2.5/LM236-2.5 and LM336-2.5 integrated cir­ cuits are precision 2.5V shunt regulator diodes. These monolithic IC voltage references operate as a low-tempera­

74LS139PC

Abstract: 74LS139P 74LS139DC
Contextual Info: ;'1 NATIONAL SEMICOND -CLO.GIO OSE D | bSDllPS 00b3fll? D | 139 139 T-66-21-55 CONNECTION DIAGRAM P IN O U T 54S/74S139 54LS/74LS139 A o a [I i s ] Eb A la [ 7 Î 7 ] Aob Öoa [ T 75] 1 2 ]Ö 0 b Ö 2a [ ? T ijö ib Ô 3 a [T 10] 5 2 b [? ~9~1 0 3 b DESCRIPTION — The *139 is a high speed dual t-of-4 decoder/demulti­

74AS182

Contextual Info: NATIONAL SEMICOND -CLOGIO bl Ì E~J bSDllEE QDSlbflfl T 6 501122 NATIONAL S E M I C O N D U C T O R . 61C 51688 D 7*-45-ô 7 p r e l im in a r y DM54AS182/DM74AS182 Look-Ahead Carry Generators General Description Features These circuits are high-speed, look-ahead carry gener­

Contextual Info: bSDllSb GQbS57Q 342 « N S C 3 51E » S 8 CM o E Z National Semiconductor NATL SEMICOND MEMORY 7 NMC27C64 65,536-Bit (8192 X 8) CMOS EPROM General Description Features The NMC27C64 is a 64K UV erasable, electrically repro­ grammable and one-time programmable (OTP) CMOS

Contextual Info: NATIONAL SENICOND -CLOGIO D5E D I bSDllSS 258 I T-66-21-51 C O N N E C T IO N D IA G R A M P IN O U T A 54S/74S258 54LS/74LS258 s QUAD 2-IN P U T MULTIPLEXER With 3-State Outputs D E S C R IP T IO N — The '258 is a quad 2-input m ultiplexer with 3-state outputs.

octal tri state buffer ic

Abstract: 74als243
Contextual Info: NATIONAL SEMICOND {LOGIC} IDE D | bSDliaa GGbkSME 1 | DM54ALS242B/DM74ALS242B/ DM54ALS243A/DM74ALS243A Quad TRI-STATE Bidirectional Bus Drivers General Description Features These octal TRI-STATE® bus drivers are designed to pro­ vide the designer with flexibility in implementing a bus inter­