8355F
Abstract: 130C JESD22
Contextual Info: Cypress Semiconductor Package Qualification Report QTP# 99331 VERSION 2.0 December, 2000 48 Lead Fine Pitch Ball Grid Array FBGA 7mm x 8.5mm ASE Taiwan CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA: Ed Russell Reliability Director (408) 432-7069 Kim-Ngan Nguyen
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BA36B
Abstract: fBGA 80 package
Contextual Info: Package Diagrams Ball Grid Array Packages 36-Ball Thin BGA BA36A 51-85099-B 1 Package Diagrams 36-Ball 7.00 mm x 8.5 mm x 1.2 mm Thin BGA BA36B 51-85105-*C 2 Package Diagrams 42-Ball FBGA (7.0 x 5.0 x 1.2 mm) BA42 51-85139-*C 3 Package Diagrams 48-Ball (8.0 x 14.0 x 1.1 mm) Thin BGA BA47
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36-ballba36a51-85099-bba36b+542-ball48-ballba48a51-85096-dfbga 80 package
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CY7C1069AV33
Abstract: CY7C1069AV33-10ZI CY7C1069AV33-10BAC CY7C1069AV33-10BAI CY7C1069AV33-10ZC CY7C1069AV33-12BAC CY7C1069AV33-12BAI CY7C1069AV33-12ZC CY7C1069AV33-12ZI
Contextual Info: CY7C1069AV33 PRELIMINARY 2M x 8 Static RAM Features device is accomplished by enabling the chip by taking CE1 LOW and CE2 HIGH and Write Enable (WE) inputs LOW. • High speed — tAA = 10 ns • Low active power — 180 mW (max.) • Operating voltages of 3.3 ±0.3V
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cy7c1069av33cy7c1069av33-10zicy7c1069av33-10baccy7c1069av33-10bai+5cy7c1069av33-10zccy7c1069av33-12baccy7c1069av33-12baicy7c1069av33-12zccy7c1069av33-12zi
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CY7C1061AV25
Abstract: CY7C1061AV25-8ZC CY7C1061AV25-8ZI CY7C1061A CY7C1061AV25-10BAI
Contextual Info: CY7C1061AV25 PRELIMINARY 1M x 16 Static RAM Features specified on the address pins A0 through A19 . If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19).
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CY7C1061
Abstract: CY7C1061AV33 CY7C1061AV33-8ZC CY7C1061AV33-8ZI CY7C1061AV33-8BAI CY7C1061AV33-12ZI
Contextual Info: CY7C1061AV33 1M x 16 Static RAM Features specified on the address pins A0 through A19 . If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). • High speed
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CY7C1061
Abstract: CY7C1061AV25 CY7C1061AV25-8ZC CY7C1061AV25-8ZI
Contextual Info: CY7C1061AV25 PRELIMINARY 1M x 16 Static RAM Features specified on the address pins A0 through A19 . If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19).
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CY7C1061AV
Abstract: CY7C1061AV33-10ZI CY7C1061AV33-12BAI
Contextual Info: CY7C1061AV33 1M x 16 Static RAM Features specified on the address pins A0 through A19 . If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). • High speed
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cy7c1069av33-10zc
Abstract: CY7C1069AV33
Contextual Info: CY7C1069AV33 2M x 8 Static RAM Features • High speed — tAA = 8, 10, 12 ns • Low active power — 1080 mW max. • Operating voltages of 3.3 ± 0.3V • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs
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CY7C1069AV33-10ZI
Abstract: CY7C1069AV33 CY7C1069AV33-10BAC CY7C1069AV33-10BAI CY7C1069AV33-10ZC CY7C1069AV33-8BAC CY7C1069AV33-8BAI CY7C1069AV33-8ZC CY7C1069AV33-8ZI BA48G
Contextual Info: CY7C1069AV33 2M x 8 Static RAM Features • High speed — tAA = 8, 10, 12 ns • Low active power — 1080 mW max. • Operating voltages of 3.3 ± 0.3V • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs
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Contextual Info: CY7C1061AV33 PRELIMINARY 1M x 16 Static RAM Features specified on the address pins A0 through A19 . If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19).
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CY7C1069AV33
Contextual Info: CY7C1069AV33 PRELIMINARY 2M x 8 Static RAM Features • High speed — tAA = 8, 10, 12 ns • Low active power — 1080 mW max. • Operating voltages of 3.3 ± 0.3V • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs
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CY7C1061AV33-10ZI
Abstract: CY7C1061 CY7C1061AV33 CY7C1061AV33-10ZC CY7C1061A
Contextual Info: PRELIMINARY CY7C1061AV33 1M x 16 Static RAM Features specified on the address pins A0 through A19 . If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19).
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