BSG112B Search Results

BT 1610 circuit

Abstract: BT 1610 b0613 B3316
Contextual Info: 100166 NATIONAL SEttlCOND LOGIC blE D • bSG112B DQ 7Seìh7 HT3 ■ NSCl Not Intended For New Designs 33 Semiconductor National T -Y W 7 100166 9-Bit Comparator General Description The 100166 is a 9-bit magnitude comparator which com­ pares the arithmetic value of two 9-bit words and indicates

Contextual Info: DS75154 NATL SEHICON]> MEMORY bflE D bSG112b DGbTDMl 34^ 03 National • U fl Semiconductor DS75154 Quad Line Receiver General Description The DS75154 is a quad monolithic line receiver designed to satisfy the requirements o f the standard interface between

NMC93C46M8

Abstract: NMC93C06N nmc93c46 NMC9306 NMC9346 NMC93C56 NMC93C66 NMC93C06EN
Contextual Info: NATL S EMI COND MEMORY 3IE D b S O iiat. 001,3451 b National Semiconductor O <o CO o NMC93C06/C46 256-Bit/1024-Bit Serial Electrically Erasable Programmable Memory General Description Compatibility with Other Devices The NMC93C06/NMC93C46 are 256/1024 bits of CMOS

NM95MS15

Abstract: NM95MS15S SA10 SA11 SA12
Contextual Info: Semiconductor PRELIMINARY February 1996 NM95MS15 Plug and Play Front-End Device for ISA-Bus Systems General Description Features The NM95MS15 is one of the family of single chip solutions designed to provide complete Plug and Play capability for ISA bus systems. The NM95MS15 includes the necessary

NM29A040

Abstract: NM29A040M NM29A040V V28A 000E8H
Contextual Info: August 1995 S e m i c o n d u c t o r N M 29A 040 4-M bit CM OS Serial FLASH E2PROM General Description Features The NM29A040 is a 4-Mbit Flash memory designed with a MICROWIRE serial interface. Ail of the features of the device are designed to provide the most cost effective solu­

lcd 30 pin diagram lvds

Abstract: lcd 40 pin diagram lvds lvds 20 pin lcd panel 24 bit lvds lcd interface pin connection lvds cable DS90CF563 DS90CF563MTD DS90CF564 DS90CF564MTD MTD48
Contextual Info: DS90CF563/DS90CF564 & National Semiconductor PRELIMINARY DS90CF563/DS90CF564 LVDS 18-Bit Color Flat Panel Display FPD Link—65 MHz General Description The DS90CF563 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signalling)

Contextual Info: NATIONAL SENICOND -CLOGIC} IDE D | bSDliaS T - 5 7 0 | - / / MM54HC4316/MM74HC4316 Quad Analog Switch with Level Translator General Description Features These devices are digitally controlled analog switches im­ plemented in advanced silicon-gate CMOS technology.

27CP128

Abstract: 27CP128Q250 27C256 General Semiconductor 27cp128q 27CP128Q250/883
Contextual Info: NATL S E M I C O N D 31E D MEMORY March 1989 "7= Ì & - / Ì - 2 9 27CP128 131,072-Bit (16,384 x 8) UV Erasable CMOS PROM Military Qualified General Description Features The 27CP128 is a high-speed 128K UV erasable and electri­ cally reprogrammable CMOS EPROM, ideally suited for ap­

MM53C200

Abstract: ENCODER IC
Contextual Info: NATL S E MICOND MEMORY STE ]) • bSQUHb D D b b T l4S 45Ü « N S C S " 7 ^ 0 7 - 3 / ' 5 / National Semiconductor Ä 5 «» June 1989 MM53C200/201 Encoder/Decoder General Description Operation The Encoder/Decoder is an M2CMOS Digital Code Trans­ mitter-Receiver system.

Contextual Info: 899A N AT IONAL SEMICONJ L06IC) tlE D • bS01122 007353^ 'JOS M N S C l T - ä 2-;?äH 3 National Semiconductor 74FCT899A 9-Bit Latchable Transceiver with Parity Generator/Checker General Description Features The ’FCT899A is a 9-bit to 9-bit parity transceiver with trans­

ds14196wm

Abstract: DS14185 DS14196 GD75323 SN75196
Contextual Info: • bSQ112t. 007S1D3 755 ■ _ October 1996 DS14196 EIA/TIA-232 5 Driver x 3 Receiver General Description Features The DS14196 is a live driver, three receiver device which conforms to the EIA/TIA-232-E and the ITU-T V.28 stan­ dards. The flow-through pinout facilitates simple non-crossover

MES 60 BZ

Abstract: cn/A/U 237 BG
Contextual Info: r, i S e m i c o n d u c t o r November 1995 DS3875 Futurebus+ Arbitration Controller General Description The DS3875 Futurebus+ Arbitration Controller is a member of National Semiconductor’s Futurebus+ chip set designed specifically for the IEEE 896.1 Futurebus+ standard. The

VHC157

Contextual Info: STE D t>5Q115b □ Gbb'ikS 53T INational February 1993 I Semiconductor 54VHC/74VHC157 Quad 2-Input Multiplexer General Description Features The VHC157 is an advanced high speed CMOS Quad 2-Channel Multiplexer fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent

NMC27C512AN

Abstract: NMC27C512ANE250
Contextual Info: NATL SEMICOND MEMORY b S G l l S b DOfc.3412 7 31E I) m National ¿¡A Semiconductor PRELIMINARY ~ 7 -V & ‘ / 3 '< 3 S General Description Features The NMC27C512AN is a high-speed 512k UV one time pro­ grammable CMOS EPROM, Ideally suited for applications

GAL Gate Array Logic

Abstract: fdk id GAL20V8A
Contextual Info: NATL S E M I C O N D MEMORY 31E D bSQHSb ÛOb423b PRELIMINARY GAL20V8A Generic Array Logic T—46—1 3-47 General Description The NSC E2CMOStm GAL device combines a high per­ formance CMOS process with electrically erasable floating gate technology. This programmable memory technology

Fairchild 9614

Contextual Info: NATL SEMICON.P MEMORY bflf ]> • bSDHSb GGbTBHfl 44b DS55114/DS75114 Dual Differential Line Drivers G eneral Description Features The DS55114/DS75114 dual differential line drivers are de­ signed to provide differential output signals with high current

11zs1

Abstract: NM93C14 NM93C14TM8 11zs1-8
Contextual Info: NM93C13/C14 256-/1024-Bit Serial EEPROM General Description Features The NM93C13/C14 is 256/1024, respectively, bits of CMOS electrically erasable memory divided into 16/64 16bit registers. They are fabricated using National Semicon­ ductor’s floating-gate CMOS process for high speed, high

NMC87C257QE200

Abstract: 27C256 NMC27C256
Contextual Info: NMC87C257 National éLm Semiconductor NMC87C257 262,144-Bit 32K x 8 CMOS EPROM with On-Chip Address Latches General Description Features The NMC87C257 is a CMOS EPROM, ideally suited for ap­ plications where fast turnaround, pattern experimentation and low power consumption are important requirements.

NMC27C16BQ150

Abstract: 27C32 27C128 27C256 27C64 J24AQ NMC27C16B NMC27C16BQ 27128 pin diagram
Contextual Info: NMC27C16B National Semiconductor NMC27C16B 16,384-Bit 2048 x 8 CMOS EPROM General Description Features The NMC27C16B is a high performance 16K UV erasable and electrically reprogrammable CMOS EPROM, ideally suited for applications where fast turnaround, pattern exper­

3em smd

Abstract: s-6 diod J03A DS16F95J circuit lzl 60 c DS16F95 DS36F95 DS96F172 DS96F173 DS96F174
Contextual Info: Semiconductor DS16F95, DS36F95 EIA-485/EIA-422A Differential Bus Transceiver General Description The DS16F95/DS36F95 Differential Bus Transceiver is a monolithic integrated circuit designed for bidirectional data communication on balanced multipoint bus transmission

Contextual Info: b5Q112b NATL SEMICOND MEMORY 3 3 1E D March 1989 _ i i l Semiconductor 27C256 262,144-Bit (32,768 x 8) UV Erasable CMOS PROM Military Qualified 35-V General Description Features The 27C256 is a high-speed 256K UV erasable and electri­ cally reprogrammable CMOS EPROM, Ideally suited for ap­

Contextual Info: NATL SEMI COND HEMORY bSGUBb bflE D DOb^aflb S S T I NSC DS55107/DS75107/DS75108/DS75208 Dual Line Receivers General Description The products described herein are TTL compatible dual high speed circuits intended for sensing in a broad range of system applications. While the primary usage will be for line

Contextual Info: N a t i o n a l S e m i c o n d u c t o r DM74ALS165 8-Bit Parallel In/Serial Out Shift Register General Description The DM74ALS165 is an 8-bit serial register that, when clocked, shifts the data toward serial output, 5h - Parallel-in access to each stage is provided by eight individual direct

74HC273

Abstract: vhc 273 msc 5511 2VA5-5 VHC273 volvo D2 74VHC273 74VHC273M 74VHC273MSCX 74VHC273MX
Contextual Info: 74VHC273 Octal D Flip-Flop General Description Features The VHC273 is an advanced high speed CMOS Octal D-type flip-flop fabricated with silicon gate CMOS technolo­ gy. It achieves the high speed operation similar to equiva­ lent Bipolar Schottky TTL while maintaining the CMOS low