AXCELERATOR FPGAS Search Results

lxt971

Abstract: pm5350 actel PLL schematic LXT971 SCHEMATIC LXT1000 LXT9763 PowerQUICC high speed connector
Contextual Info: Product Brief Axcelerator Evaluation Platform The Axcelerator evaluation platform has been designed to demonstrate the unique capabilities of Actel’s new Axcelerator family of FPGAs. It provides the designers an easy to use hardware platform to evaluate and test various

FBGA 896

Abstract: AX125 AX2000 CS180 IDTQS32X2384 Silicon Sculptor II Axcelerator Family FPGAs
Contextual Info: Axcelerator Family FPGAs Detailed Specifications Operating Conditions Table 2-1 lists the absolute maximum ratings of Axcelerator devices. Stresses beyond the ratings may cause permanent damage to the device. Exposure to Absolute Maximum rated conditions for extended periods may affect device

AX125

Abstract: AX2000 CS180 IDTQS32X2384 Silicon Sculptor II Axcelerator FPGAs Axcelerator Family FPGAs
Contextual Info: Axcelerator Family FPGAs Detailed Specifications Operating Conditions Table 2-1 lists the absolute maximum ratings of Axcelerator devices. Stresses beyond the ratings may cause permanent damage to the device. Exposure to Absolute Maximum rated conditions for extended periods may affect device

CQFP 256 PIN actel

Contextual Info: Axcelerator Family FPGAs Detailed Specifications Operating Conditions Table 2-1 lists the absolute maximum ratings of Axcelerator devices. Stresses beyond the ratings may cause permanent damage to the device. Exposure to Absolute Maximum rated conditions for extended periods may affect device

RTAX1000S

Abstract: RTAX2000S CQFP352 RTAX-S jtag pull-up resistor 10K RTAX2000 RTAX-S library RAM EDAC SEU AC173 ACTEL
Contextual Info: Application Note AC173 Differences Between RTAX-S/SL and Axcelerator Introduction RTAX-S/SL is Actel's latest FPGA family designed for space applications and is a derivative of the Actel Axcelerator FPGA family. The RTAX-S/SL architecture is based on Actel's multi-featured, high-density AX

RTAX-S lvds

Abstract: ASK transmitter and receiver pair AN-1040 AN-1059 vhdl code for lvds driver
Contextual Info: Application Note AC288 Using LVDS for Actel's Axcelerator and RTAX-S/SL Devices Introduction This application note describes the Low Voltage Differential Standard LVDS I/O capabilities of Actel's Axcelerator and RTAX-S/SL device families. The application note begins by describing the LVDS signaling

types of multipliers

Abstract: 4-input-XOR 4 INPUT XOR block diagram 8 bit booth multiplier Tx chain 32 bit adder 16-bit adder 16 bit adder AX500 A54SX32A
Contextual Info: Application Note AC163 Axcelerator Carry-Connect Macros I n tro du ct i on The C-cell features the following Figure 1 : The Axcelerator dedicated carry-chain logic offers a very compact solution for implementing arithmetic functions without sacrificing performance. The AX architecture, on

fifo controller

Abstract: RTAX-S
Contextual Info: Application Note AC228 EMPTY and FULL Flag Behaviors of the Axcelerator FIFO Controller Introduction The purpose of this application note is to specifically illustrate the following two behaviors of the FULL and EMPTY flags: • The Axcelerator and RTAX-S FIFO controller deasserts the EMPTY flag for two read clock cycles

CCGA

Abstract: 896-Pin 624 CCGA AD 149 AE9 FBGA 63 AX125 FBGA 896
Contextual Info: Axcelerator Family FPGAs Package Pin Assignments 180-Pin CSP A1 Ball Pad Corner 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P Figure 3-1 • 180-Pin CSP Bottom View v2.3 3-1 Axcelerator Family FPGAs 180-Pin CSP 180-Pin CSP AX125 Function Pin Number

FlashPro3

Abstract: Libero Core8051s actel core 8051 project Core8051 AC354 actel core 8051 AX250-PQ208 FLASHPRO4 80C31
Contextual Info: Application Note AC354 Core8051s Debugging in Axcelerator and RTAX-S Device Table of Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . Core8051s Debug Configuration . . . . . . . . . . . . . Design Example . . . . . . . . . . . . . . . . . . . . . .

64 bit booth multiplier

Abstract: block diagram 8 bit booth multiplier 2114 ram loader booth multiplier RLF100-11/12/Modified Booth Multipliers
Contextual Info: Application Note AC218 Using Axcelerator RAM as Multipliers Introduction Multiplication is one of the more area-intensive functions in FPGAs. Traditional multiplication techniques use the digital equivalent of longhand multiplication, which we learned in elementary school. These

Silicon Sculptor II

Contextual Info: Axcelerator Family FPGAs Key Features 350 MHz System/500 MHz Internal Performance 2 Million Equivalent System Gates Up to 339k bits Embedded SRAM with FIFO Logic Flexible Multiple Standard I/Os Innovative 64 bit PerPin FIFO 8 Embedded 1 GHz PLLs Secure Nonvolatile

verilog code for cdma transmitter

Abstract: Actel pdf on gsm Actel pdf on radio emitter CS180 AC212 AX250-PQ208 testbench of a transmitter in verilog
Contextual Info: Application Note AC212 Designing a SuperClock with an Axcelerator Device Introduction Many board designs today require complex clocking schemes involving multiple frequencies and phases. Semiconductor manufacturers have developed a multitude of products to address these situations, from

Contextual Info: v2 .1  Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates

896-Pin

Abstract: smartpower IO290 Axcelerator Family FPGAs
Contextual Info: v2.2 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates

MA 6013

Contextual Info: v2.5 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates

avnet

Abstract: ProASIC3 A3P250 A3P250 APA075 AX125
Contextual Info: AvnetCore: Datasheet Version 1.0, July 2006 UTOPIA Level 2 PHY Features: — Supports Actel Axcelerator devicesI/O Peripherals — Compliant with ATM Forum af-phy-0017.000 and af-phy-0039.000 — Supports up to 31 PHYs MC-ACT-UL2PHY Transmit Interface ING_CLK

b h21

Contextual Info: Revision 18 Axcelerator Family FPGAs Leading-Edge Performance • • • • 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates

AX125

Abstract: AX2000 CQ208 CQ256 FG256 FG324 PQ208 AX2000-CQ256
Contextual Info: Revision 17 Axcelerator Family FPGAs Leading-Edge Performance • • • • 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates

ACTEL CCGA 1152 mechanical

Abstract: AX125 AX2000 CQ208 CQ256 CS180 FG256 PQ208 Trd16 Axcelerator Family FPGAs
Contextual Info: v2.8 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates

ACTEL CCGA 1152 mechanical

Abstract: CS180 antifuse AX125 AX2000 CQ208 CQ256 FG256 PQ208 ACTEL CCGA 624 mechanical
Contextual Info: v2.8 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates

ACTEL CCGA 1152 mechanical

Abstract: lga 4x4 footprint AX125 AX2000 CQ208 CS180 FG256 PQ208 624-Pin tx 434
Contextual Info: v2.7 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates

GCLR

Abstract: 676P Axcelerator Family FPGAs
Contextual Info: v2.4 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates

AF4 din 74

Abstract: AF2.5 din 74 diode t25 4 g8 Axcelerator Family FPGAs
Contextual Info: v2.5 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates