AX4000 Search Results

Contextual Info: xr PRELIMINARY XRT79L71 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - CC/HDLC ARCHITECTURAL DESCRIPTION NOVEMBER 2005 GENERAL DESCRIPTION The XRT79L71 is a single channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller and Line Interface Unit with Jitter

PM5357-BI

Abstract: cpci backplane schematic plx vhdl code PCI9050-1 F 1uH smt unimax of thumbwheel switch LT1066 CC621660B PM5357-BI-P
Contextual Info: PMC-Sierra, Inc. PRELIMINARY PM5357 S/UNI-622-POS REFERENCE DESIGN PMC-1981070 ISSUE 2 S/UNI-622-POS REFERENCE DESIGN PM5357 S/UNI-622-POS SATURN USER NETWORK INTERFACE 622-POS REFERENCE DESIGN PROPRIETARY AND CONFIDENTIAL PRELIMINARY ISSUE 2: FEBRUARY 2000

IXF6012

Abstract: IXP1200 IXP1240 64Kentry
Contextual Info: IXP12xx ATM OC12/Ethernet IP Router Example Design Performance and Headroom Analysis April, 2002 Document Number: 301144-001 Version 1.0, 4/10/02 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or

TBA 2822

Abstract: 6c21 ALARM CODE MPH-E13
Contextual Info: PMC-Sierra, Inc. APPLICATION NOTE PMC-970239 ISSUE 1 PM6344 EQUAD QUADRUPLE E1 FRAMER PM6344 EQUAD MEETING ETS 300 011 REQUIREMENTS WITH THE EQUAD Issue 1: March 1998 PMC-Sierra, Inc. Suite105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 415- 6000 PMC-Sierra, Inc.

AX4000

Abstract: PM3388 DDR2 sodimm pcb layout
Contextual Info: LatticeSCM SPI4.2 Interoperability with PMC-Sierra PM3388 August 2006 Technical Note TN1121 Introduction The System Packet Interface, Level 4, Phase 2 SPI4.2 is a system level interface, published in 2001 by the Optical Internetworking Forum (OIF), for packet and cell transfer between a physical layer (PHY) device and a link layer

DMO 565 R

Contextual Info: xr PRELIMINARY XRT79L71 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - ATM ARCHITECTURAL DESCRIPTION NOVEMBER 2005 GENERAL DESCRIPTION The XRT79L71 is a single channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller and Line Interface Unit with Jitter

TBA 2822

Abstract: fireberd 6000 PM6341 TS16 fireberd 6000 e1 E1 frame
Contextual Info: PMC-Sierra, Inc. APPLICATION NOTE PMC-951128 ISSUE 3 PM6341 E1XC E1 FRAMER/TRANSCEIVER PM6341 E1XC MEETING ETS 300 011 REQUIREMENTS WITH THE E1XC Issue 3: March 1998 PMC-Sierra, Inc. Suite105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 415- 6000 PMC-Sierra, Inc.

7C241

Abstract: fireberd 6000 7C221 EQUAD PM6344 TS16 E1 frame TBA 2822 7C322
Contextual Info: PMC-Sierra, Inc. APPLICATION NOTE PMC-970239 ISSUE 2 PM6344 EQUAD QUADRUPLE E1 FRAMER PM6344 EQUAD MEETING ETS 300 011 REQUIREMENTS WITH THE EQUAD Issue 2: 1998 PMC-Sierra, Inc. Suite105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 415- 6000 PMC-Sierra, Inc.

dmo 465

Contextual Info: xr PRELIMINARY XRT79L71 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - PPP ARCHITECTURAL DESCRIPTION DECEMBER 2005 GENERAL DESCRIPTION The XRT79L71 is a single channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller and Line Interface Unit with Jitter

block diagram for ic 7404 input id

Abstract: dmo 365 r 17X17 GR-253 GR-499-CORE MPC860 XRT79L71 XRT79L71IB C5339 equalizer ic 5218
Contextual Info: PRELIMINARY XRT79L71 1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE OCTOBER 2010 GENERAL DESCRIPTION The XRT79L71 is a single channel, integrated DS3/ E3 framing controller and Line Interface Unit with Jitter Attenuator that is designed to support Frame processing. For Clear-Channel Framer applications, this

Serial DB9 to RJ12

Abstract: RJ12 db9 RJ12 to RS232 XP-40 CX29704 CX29704TAP MPC8260 XC2S50E-FT256
Contextual Info: CX29704 OptiPHY-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer EVM User Manual 29704-EVMD-001-C June 2005 CX29704 EVM User Manual OptiPHY-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer Revision History Revision Level Date C Released June 2005 B Advance November 2004