PM3388 Search Results

AX4000

Abstract: PM3388 DDR2 sodimm pcb layout
Contextual Info: LatticeSCM SPI4.2 Interoperability with PMC-Sierra PM3388 August 2006 Technical Note TN1121 Introduction The System Packet Interface, Level 4, Phase 2 SPI4.2 is a system level interface, published in 2001 by the Optical Internetworking Forum (OIF), for packet and cell transfer between a physical layer (PHY) device and a link layer

Contextual Info: 5: 25 AM S/UNI10xGE Telecom Standard Product Data Sheet Released 10 Ma y ,2 00 5 02 :2 PM3388 Tu es da y, S/UNI-10xGE d of ag er rt on Ten-Port Gigabit Ethernet Controller Do wn lo a de d by sa tis h Data Sheet Proprietary and Confidential Released Issue No. 6: September 2002

tt6061

Abstract: dh6af pm3388fi PM3011 31ab marking PM3388H-FI
Contextual Info: 8: 20 PM S/UNI10xGE Telecom Standard Product Data Sheet Released ru sd ay ,0 7F eb S/UNI 10xGE ar y, 20 07 06 :5 PM3388 In co n W ed ne Ten-Port Gigabit Ethernet Controller Proprietary and Confidential Released Issue No. 8: January, 2007 Do wn l oa de d by

PM8388

Abstract: 200WN
Contextual Info: 0: 14 PM S/UNI10xGE Telecom Standard Product Data Sheet Released Mo nd ay ,1 3M ar S/UNI 10xGE ch ,2 00 6 10 :1 PM3388 rtm in er In co n Ten-Port Gigabit Ethernet Controller Proprietary and Confidential Released Issue No. 7: February 2006 Do wn l oa de d by

PM3388

Abstract: ATMF0161 OIF2000 PM5390 ATP3 ATP01
Contextual Info: PM3388 S/UNI -10xGE Preliminary 10-Port Gigabit Ethernet Controller FLOW CONTROL • Option to support IEEE 802.3-1998 flow control at each Ethernet port. • Programmable watermarks for full/empty/starving FIFO conditions. • Automatic generation of pause frames

Contextual Info: 0: 41 PM S/UNI10xGE Telecom Standard Product Data Sheet Released ob sd ay ,2 8O ct S/UNI-10xGE er ,2 00 4 02 :3 PM3388 er In co n Th ur Ten-Port Gigabit Ethernet Controller Proprietary and Confidential Released Issue No. 6: September 2002 Do wn lo ad ed by

ATP1

Abstract: ATMF0161 PM5390 PM3388 OIF2000
Contextual Info: PM3388 S/UNI -10xGE Preliminary FEATURES da STATISTICS PACKAGING • Flip Chip technology • Implemented in low power 1.8 V CMOS technology with 3.3 V compatible I/O. • Industrial temperature range -40 °C to +85 °C . • Provides a standard 5 signal P1149.1

LP-UNEQ

Abstract: JT-G707 AU-AIS pm5350 PM5345 PM5346 PM5347 PM5390 UNI-9953 JESD22 A113
Contextual Info: Knowledge Base Items PM5390 S/UNI-9953 PM5390 S/UNI-9953 Knowledge Base Items Proprietary and Confidential April 9, 2002 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2020349 April 9, 2002 1 Knowledge Base Items

Contextual Info: :1 0: 33 PM S/UNI-1x10GE ASSP Telecom Standard Product Data Sheet Released 3M ar ch ,2 00 6 10 PM3392 Mo nd ay ,1 S/UNI 1x10GE Data Sheet Proprietary and Confidential Released Issue No. 6: February 2006 Do wn l oa de d by C on te nt T ea m of Pa rtm in er

Contextual Info: :0 1: 29 PM S/UNI-1x10GE ASSP Telecom Standard Product Data Sheet Released ru ar y, 20 07 07 PM3392 ne sd ay ,0 7F eb S/UNI 1x10GE Data Sheet Proprietary and Confidential Released Issue No. 7: December, 2006 Do wn l oa de d by C on te n tT ea m of Pa rtm in

Xenon 175

Abstract: SFP LVDS altera PC680 PM5392 STM-64 SFP PM3388 PM3392 PM5390 hmzd connector SFP altera
Contextual Info: SPI-4.2 Interoperability with PMC-Sierra XENON Family in Stratix GX Devices May 2003, ver. 1.0 Introduction Application Note 228 The system packet interface level 4–phase 2 SPI-4.2 specification, defined by the Optical Internetworking Forum (OIF), is fast becoming the most

Contextual Info: 8: 41 PM S/UNI-1x10GE ASSP Telecom Standard Product Data Sheet Released ob er ,2 00 4 02 :2 PM3392 ur sd ay ,2 8O ct S/UNI-1x10GE Data Sheet Proprietary and Confidential Released Issue No. 5: October 2002 Do wn lo ad ed by C on te n tT ea m of Pa rtm in er

PM3393

Abstract: 330 e17 smd tantalum capacitor marking code
Contextual Info: 9: 40 PM S/UN 1x10GE XP ASSP Telecom Standard Product Data Sheet Released ch ,2 00 6 10 :0 PM3393 Mo nd ay ,1 3M ar S/UNI 1x10GE XP Data Sheet Proprietary and Confidential Released Issue 5: February 2006 Do wn l oa de d by C on te nt T ea m of Pa rtm in

PMC-2020518

Abstract: saturn st 1518 su384 RXLFI
Contextual Info: :1 8: 06 PM S/UNI-1x10GE ASSP Telecom Standard Product Data Sheet Released m be r, 20 07 10 PM3392 nd ay ,1 6S ep te S/UNI 1x10GE Data Sheet Proprietary and Confidential Released Issue No. 7: December, 2006 Do wn l oa de d by I HS Pa r ts Ma na g em en tI

Contextual Info: Soft SPI4 IP Core User’s Guide September 2010 IPUG59_01.7 Table of Contents Chapter 1. Introduction . 4 Quick Facts . 4

Contextual Info: 34 AM S/UN 1x10GE XP ASSP Telecom Standard Product Data Sheet Released be r, 20 04 06 :5 8: PM3393 y, 14 Se pt em S/UNI 1x10GE XP Data Sheet Proprietary and Confidential Released Issue 4: June 2003 Do wn lo ad ed by Co nt e nt Te a m of P ar tm in er In

PM8358-NI

Abstract: M0330 196-pin bga footprint 10G serdes PM8358 CX4 connector PM8355 10G serdes 2.5 xaui wireles ethernet PM8354
Contextual Info: Signal Integrity There’s more than Meets the Eye PMC-Sierra’s Multi-Gigabit Serial Expertise • Core to PMC-Sierra Business • >65% of PMC products integrate SERDES • History delivering production hardened SERDES • Discrete and highly integrated products such as:

Am386

Contextual Info: 34 AM S/UN 1x10GE XP ASSP Telecom Standard Product Data Sheet Released 10 Ma y ,2 00 5 02 :2 4: PM3393 Tu es da y, S/UNI 1x10GE XP Data Sheet Do wn lo a de d by sa tis h d of ag er rt on SATURN® User Network Interface For 10 Gigabit Ethernet LAN PHY with XAUI

PM3392

Abstract: M29730 PM3388 PM5390 STS-48 10gb TX drive
Contextual Info: Flexbus-4 / POS-PHY Level-4 Bridge Core for Virtex -II November 2, 2001 Product Specification LogiCORE™ Facts Core Specifics Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 URL: www.xilinx.com/ipcenter Support: www.support.xilinx.com

marvell 88e1145

Abstract: 88E1145 ZL30145 ZL30143 PM3387 Marvell design guide RX 3E ZL30142 88E11340S S19263
Contextual Info: TECHNOLOGY GUIDE: SYNCHRONOUS ETHERNET Discovery Questions to Help Learn a Customer’s Requirements Discover Zarlink’s Synchronization Solutions Zarlink Synchronous Ethernet devices are designed to pro- General vide complete physical layer synchronization for packet

altera marking Code Formats Cyclone 2

Abstract: verilog code for spi4.2 to fifo vhdl 4-bit binary calculator cyclone FPGA 144 EP3C40F780C6 EP4SGX230DF29C3ES EP4SGX70 PM3388 EP3SE50F780 OIF-SPI4-02
Contextual Info: POS-PHY Level 4 MegaCore Function User Guide POS-PHY Level 4 MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-IPPOSPHY4-10.0 Document last updated for Altera Complete Design Suite version: Document publication date: 10.0

SGMII PCIE bridge

Abstract: RGMII to SGMII bridge SGMII RGMII bridge StrataXGS EVALUATION BOARD 88E1111 Marvell 88E1111 mdio 88E1111 jumbo GMII Marvell PHY 88E1111 Datasheet 88e1111 mii fpga ethernet sgmii
Contextual Info: f u l l y t e s t e d a n d i n t e r o p e r a b l e Lattice Ethernet Solutions Ready-to-Use Ethernet Portfolio Lattice provides customers with low cost and low power programmable solutions that are ready-to-use right out of the box. A full suite of tested and interoperable solutions is available for Ethernet

LINEAR TECNOLOGY SMD 490

Abstract: efd k14 marking y1 t4 10G Ethernet MAC chopper aa26 8B10B PM3392 10GMAC PMC-2021098 PM3393
Contextual Info: 22 AM S/UN 1x10GE XP ASSP Telecom Standard Product Data Sheet Released 0A pr il, 20 05 06 :0 5: PM3393 Su nd ay ,1 S/UNI 1x10GE XP Data Sheet Proprietary and Confidential Released Issue 4: June 2003 ow n lo ad ed by Am r Ma ns o ur of S ilic on E xp er tT

EP3SE50F780

Abstract: PM3388 EP3C40F780C6 EP4SGX230DF29C3ES EP4SGX70 verilog code for spi4.2 interface altddio_out EP3SE50F
Contextual Info: POS-PHY Level 4 MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com MegaCore Version: Document Date: 9.1 November 2009 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other