N110
Abstract: N111 P267 ATL60 DLY1500 DLY2000 P109 P123 P162 TI N268
Contextual Info: DLY1500 ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: Delay buffer 1.5 ns Truth Table: I | O -0 | 0 1 | 1 at60Cells I DLY1500 O VDD! VDD! p P5 p p P30 VDD! p P19 P6 p p P0 VDD! p P18 p P7 p P17 P25<0:1> I O n n N1 n N8 n N16 N24 n N9 VSS!
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ATL60
Contextual Info: HLD1 ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: Bus hold cell Truth Table: X | X -0 | weak0 1 | weak1 at60Cells HLD1 X VDD! p P0 p P10 p P8 VSS! p P33 p P7 p P34 X n N6 n N24 n N25 VDD! n N12 n N26 n N15 VSS! VDD! p P31 n N19 VSS! / $Revision: 1.27 $
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n37 transistor
Abstract: n38 transistor P41 transistor P42 transistor ATL60 n38P
Contextual Info: BUF2T ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: 2x Tri State bus driver with active high enable Truth Table: E I | O -0 X | Z 1 0 | 0 1 1 | 1 at60Cells BUF2T O I E VDD! p P11 VDD! p P4 n N3 p P12 VSS! I O n N5 VDD! N13 VSS! n p VDD! P0
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ATL60
Contextual Info: CLA7X ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: 7 input carry lookahead Truth Table: at60Cells A A B C D E F G | O -X X X X X X 1 | 0 X X X X 1 1 X | 0 X X 1 1 X 1 X | 0 1 1 X 1 X 1 X | 0 X X X X X 0 0 | 1 X X X 0 0 X 0 | 1
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P62d
Abstract: ATL60 1147-000
Contextual Info: LAT ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: LATCH Truth Table: H D | Q T+1 -0 0 | 0 1 | 1 1 X | Q(T) at60Cells H LAT D Q VDD! VDD! p P58 p P53 p P62 D Q n n N59 N52 N63 n VSS! VSS! VDD! N56 n p P57 p P65 VDD! n VDD!
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ATL60
Abstract: INV10
Contextual Info: INV1 ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: 1x inverter Truth Table: INV1 at60Cells1X I I | O -0 | 1 1 | 0 O VDD! p P5 I O n N4 VSS! / $Revision: 1.27 $ Tue Apr 23 12:17:53 1996
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N117
Abstract: N294 N280 N109 15 N119 CMOS N48 N147 N315 P115 transistor p88
Contextual Info: DFF ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: D flip-flop Truth Table: CLK D | Q T+1 -RE 0 | 0 RE 1 | 1 FE X | Q(T) at60Cells CLK DFF D Q VDD! VDD! n N73 p n N71 P18 N26 p P34 n VSS! VDD! n N25 p p p n P33 N54 P5 p P13 P8
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CMOS GATE ARRAY buf8
Abstract: ATL60 P41N
Contextual Info: BUF1 ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: 1x buffer Truth Table: at60Cells 1X I I | O -0 | 0 1 | 1 BUF1 O VDD! p VDD! p P0 P2 I O n n N3 N4 VSS! VSS! / $Revision: 1.27 $ Tue Apr 23 12:10:29 1996
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ATL60
Abstract: N109
Contextual Info: NOR2 ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: 2 input NOR Truth Table: A B | O -0 0 | 1 1 X | 0 X 1 | 0 at60Cells A NOR2 O B VDD! p A P2 p B P0 O n n N10 VSS! / $Revision: 1.27 $
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0044300
Abstract: ATL60 P102 3-input NAND gate
Contextual Info: NAN2 ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: 2 input NAND Truth Table: A B | O -0 X | 1 X 0 | 1 1 1 | 0 at60Cells B NAN2 O A VDD! p VDD! p P4 P13 O n B N3 n A N10 VSS! / $Revision: 1.27 $
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P103
Abstract: P133 ATL60 N132 MUX8n 0020700 P107N 08155 PP201 1251-1-1
Contextual Info: MUX2 ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: 2:1 MUX Truth Table: S | O -0 | I0 1 | I1 at60Cells S MUX2 I0 O I1 VDD! p P14 S n N3 VSS! VDD! p P20 p P23 I0 VDD! n N6 N22 n p P32 VSS! O n VDD! N34 p P16 p P21 I1 n N25 VSS! VDD! N29
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40669
Abstract: 8618 N219 05612 0505790 450380 N249 n252 N255 p206
Contextual Info: DEC4 ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: 2:4 decoder Truth Table: S1 S0 | D3 D2 D1 D0 -0 0 | 1 1 1 0 0 1 | 1 1 0 1 1 0 | 1 0 1 1 1 1 | 0 1 1 1 at60Cells DEC4 S0 D0 S1 D2 D1 D3 VDD! VDD! p p VDD! P95 p P97 D0 P92
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AOI222
Abstract: AOI23 AOI22 AOI2223H AOI222H AOI22H AOI2223 ATL60
Contextual Info: AND2 ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: 2 input AND Truth Table: A B | O -0 0 | 0 0 1 | 0 1 0 | 0 1 1 | 1 at60Cells B AND2 O A VDD! p VDD! p P2 VDD! p P0 P1 O n B n N3 N5 n A N4 VSS! VSS! / $Revision: 1.27 $
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voltage level shifter
Abstract: ATL60 0801500 3P110
Contextual Info: LSCC ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: Voltage level shifter Truth Table: I | O1 O2 -0 | 0 1 1 | 1 at60Cells VDDIN VDDOUT O1 LSCC O2 I VDDIN VDDOUT p p P120<0:4> P66 VDDOUT p P17 VDDIN p p p P4 I P37 P48 n n N3 n N47 N46
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ATL60
Abstract: N100 Q20Q20 Full Adder
Contextual Info: ADD3X ATL60 CMOS Gate Array cell data sheets 3.3 DESCRIPTION: 1bit full adder with buffered outputs Truth Table: P Q CI | SO CO -0 0 0 | 0 0 0 0 1 | 1 0 0 1 0 | 1 0 0 1 1 | 0 1 1 0 0 | 1 0 1 0 1 | 0 1 1 1 0 | 0 1 1 1 1 | 1 1 SO P ADD3X Q CO
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