ASSOCIATIVE CACHE Search Results

VDD33

Abstract: asa16
Contextual Info: MN103E0600YD Type MN103E0600YD under development Instruction Cache 16 K-byte (4-way, set-associative) Data Cashe 16 K-byte (4-way, set-associative) Package MLGA239-C-1111 Minimum Instruction Execution Time 7.5 ns (at 1.8 V tolerance = ±5% , 133 MHz) Interrupts

pwm sa8

Abstract: MN103E0600YD SD21 SD27 SD31
Contextual Info: MN103E0600YD Type MN103E0600YD under development Instruction Cache 16 K-byte (4-way, set-associative) Data Cashe 16 K-byte (4-way, set-associative) Package MLGA239-C-1111 Minimum Instruction Execution Time 7.5 ns (at 1.8 V tolerance = ±5% , 133 MHz) Interrupts

Contextual Info: MN103E0600YD Type MN103E0600YD under development Instruction Cache 16 K-byte (4-way, set-associative) Data Cashe 16 K-byte (4-way, set-associative) Package MLGA239-C-1111 Minimum Instruction Execution Time 7.5 ns (at 1.8 V tolerance = ±5% , 133 MHz) Interrupts

PX-ODB-AMT-20

Contextual Info: MN103E0600YD Type MN103E0600YD under development Instruction Cache 16 K-byte (4-way, set-associative) Data Cashe 16 K-byte (4-way, set-associative) Package MLGA239-C-1111 Minimum Instruction Execution Time 7.5 ns (at 1.8 V tolerance = ±5% , 133 MHz) Interrupts

sd2608

Abstract: 9801 nec IEEE754 MN103E010HRA MN103E040HYB pc9801 nec c bus
Contextual Info: MN103E010HRA, MN103E040HYB Type MN103E010HRA MN103E040HYB Instruction Cache 16 K-byte 4-way, set-associative Data Cashe 16 K-byte (4-way, set-associative) SRAM Used by Both Instructions and Data Package 16 K-byte BGA292-P-2727 *Lead-free FLGA424-C-1717 *Lead-free

transistor b1240

Abstract: B1240 transistor B1240 r DDR333 PAR64 PC2700 REQ64
Contextual Info: Intel 80333 I/O Processor Datasheet Product Features • ■ ■ ■ ■ ■ ■ Integrated Intel XScale® core — 500, 667 and 800 MHz — ARM* V5TE Compliant — 32 KByte, 32-way Set Associative Instruction Cache with cache locking — 32 KByte, 32-way Set Associative Data

MD-001A

Contextual Info: MN103E010HRA, MN103E040HYB Type MN103E010HRA MN103E040HYB Command Cache 16 K-byte 4-way, set-associative Data Cashe 16 K-byte (4-way, set-associative) SRAM Used by Both Instructions and Data Package 16 K-byte BGA292-P-2727 FLGA424-C-1717 7.5 ns (at 1.8 V tolerance = ± 5%, 133 MHz)

i960 Cx Instruction Set Quick Reference

Abstract: I960 hx i960 Cx Processor Instruction Set Quick Reference 80960CA 80960CF 80960HA 80960HD 80960HT 80960JA 80960JD
Contextual Info: i960 HA/HD/HT Superscalar Microprocessors PRODUCT HIGHLIGHTS • Superscalar RISC core ■ 16 Kbyte four-way set associative instruction cache ■ 8 Kbyte four-way set associative data cache ■ 2 Kbyte on-chip data RAM ■ On-chip high-speed interrupt controller

SD2608

Abstract: IEEE754 MN103E010HRA MN103E040HYB
Contextual Info: MN103E010HRA, MN103E040HYB Type MN103E010HRA MN103E040HYB Command Cache 16 K-byte 4-way, set-associative Data Cashe 16 K-byte (4-way, set-associative) SRAM Used by Both Instructions and Data Package 16 K-byte BGA292-P-2727 *Lead-free FLGA424-C-1717 *Lead-free

VDD18

Abstract: CLK48
Contextual Info: MN103E010HRA, MN103E040HYB Type MN103E010HRA MN103E040HYB Instruction Cache 16 K-byte 4-way, set-associative Data Cashe 16 K-byte (4-way, set-associative) SRAM Used by Both Instructions and Data Package 16 K-byte BGA292-P-2727 *Lead-free FLGA424-C-1717 *Lead-free

BCM4320

Abstract: BCM4318 BCM4321 BCM4309 BCM4705 BCM5397 BROADCOM BCM4320 Broadcom WLAN BCM4318 2x2 MIMO block diagram diagram of wifi wireless router
Contextual Info: BCM4705 Brief Intensi-fi Gigabit Ethernet Draft-802.11n Processor SUMMARY OF BENEFITS FEATURES • Advanced 500 DMIPS/300-MHz MIPS32® core • • • • 4-way set associative 32-KB I-Cache 2-way set associative 32-KB D-Cache 4-KB Read-Ahead Cache

SDRAM edac

Abstract: AT697 Radiation report AT697 AT697E AT697F SPARC T4-2 at697e-2h-e MQFP256
Contextual Info: Features • SPARC V8 High Performance Low-power 32-bit Architecture – 8 Register Windows • Advanced Architecture: • • • • • • • • • • • • – On-chip Amba Bus – 5 Stage Pipeline – 32 KB 4-way associative Instruction Cache – 16 KB 2-way associative Data Cache

Contextual Info: MN103E010H Type MN103E010H [ES Enginner Sample available] Command Cache 16 K-byte (4-way, set-associative) Data Cashe 16 K-byte (4-way, set-associative) SRAM Used by Both Instructions and Data Package 16 K-byte FLGA424-C-1717 7.5 ns (at 1.8 V to lerance = ± 5%, 133 MHz)

VCC15

Abstract: DDR333 M66EN PAR64 PC2700 REQ64 c 337 25 w24 B1230-03
Contextual Info: Intel 80331 I/O Processor Datasheet Product Features • ■ ■ ■ ■ ■ ■ Integrated Intel R XscaleTM Core — 500, 667 and 800 MHz — ARM* V5TE Compliant — 32 KByte, 32-way Set Associative Instruction Cache with cache locking — 32 KByte, 32-way Set Associative Data

Contextual Info: MB86932 FUJITSU SPARCIite 32-BIT RISC EMBEDDED PROCESSOR MAY 25, 1994 FEATURES • 4 0 M H z 2 5 n s/cy cle operating frequency • SPARC high perform ance R IS C architecture • 8 K by tes 2 -way set associative instruction cach e • 2 K bytes 2 - way set associative data cache

Contextual Info: MB86932_ FUJITSU 930 Series 32-BIT RISC EMBEDDED PROCESSOR M AY 25, 1994 FEATURES • 4 0 MHz 25ns/cycle operating frequency • SPARC high performance R ISC architecture • 8 Kbytes 2-way set associative instruction cache • 2 Kbytes 2-way set associative data cache

Contextual Info: Intel 80332 I/O Processor Datasheet Product Features • ■ ■ ■ ■ ■ ■ Integrated Intel XScale® core — 500, 667 and 800 MHz — ARM* V5TE Compliant — 32 KByte, 32-way Set Associative Instruction Cache with cache locking — 32 KByte, 32-way Set Associative Data

Contextual Info: Intel 80333 I/O Processor Datasheet Product Features • ■ ■ ■ ■ ■ ■ Integrated Intel XScale® core — 500, 667 and 800 MHz — ARM* V5TE Compliant — 32 KByte, 32-way Set Associative Instruction Cache with cache locking — 32 KByte, 32-way Set Associative Data

IEEE754

Abstract: MN103E010H
Contextual Info: MN103E010H Type MN103E010H [ES Enginner Sample available] Command Cache 16 K-byte (4-way, set-associative) Data Cashe 16 K-byte (4-way, set-associative) SRAM Used by Both Instructions and Data Package 16 K-byte FLGA424-C-1717 7.5 ns (at 1.8 V to lerance = ± 5%, 133 MHz)

B1210

Abstract: DDR333 M66EN PAR64 PC2700 REQ64
Contextual Info: Intel 80331 I/O Processor Datasheet Product Features • ■ ■ ■ ■ ■ ■ Integrated Intel XScale® core — 500, 667 and 800 MHz — ARM* V5TE Compliant — 32 KByte, 32-way Set Associative Instruction Cache with cache locking — 32 KByte, 32-way Set Associative Data

b1210

Abstract: intel package marking w18 PC2700 REQ64 DDR333 M66EN PAR64 intel 27394 k2640 a21v5
Contextual Info: Intel 80331 I/O Processor Datasheet Product Features • ■ ■ ■ ■ ■ ■ Integrated Intel XScale® core — 500, 667 and 800 MHz — ARM* V5TE Compliant — 32 KByte, 32-way Set Associative Instruction Cache with cache locking — 32 KByte, 32-way Set Associative Data

transistor b1240

Abstract: B1240 transistor B1240 r P12VSS CODE MARKING aa29 philips b1240 DDR333 M66EN PAR64 PC2700
Contextual Info: Intel 80332 I/O Processor Datasheet Product Features • ■ ■ ■ ■ ■ ■ Integrated Intel XScale® core — 500, 667 and 800 MHz — ARM* V5TE Compliant — 32 KByte, 32-way Set Associative Instruction Cache with cache locking — 32 KByte, 32-way Set Associative Data

3054* intel

Abstract: 80333 bad33
Contextual Info: Intel 80333 I/O Processor Datasheet Product Features • ■ ■ ■ ■ ■ ■ Integrated Intel XScale® core — 500, 667 and 800 MHz — ARM* V5TE Compliant — 32 KByte, 32-way Set Associative Instruction Cache with cache locking — 32 KByte, 32-way Set Associative Data

Contextual Info: Intel 80331 I/O Processor Datasheet Product Features • ■ ■ ■ ■ ■ ■ Integrated Intel XScale® core — 500, 667 and 800 MHz — ARM* V5TE Compliant — 32 KByte, 32-way Set Associative Instruction Cache with cache locking — 32 KByte, 32-way Set Associative Data