AS4C256 Search Results

Contextual Info: AS4C256K16E0 5V 256Kx 16 CMOS DRAM EDO Features • Refresh - 5 1 2 refresh cycles, 8 m s refresh interval - RAS-only o r CAS-before-RAS refresh o r self-refresh - Self-refresh o p tio n is available for n e w g en eratio n device • O rganization: 2 6 2 ,1 4 4 w o rd s x 16 bits

AS4C256K16F0-60JC

Abstract: ez 948 AS4C256K16F0 LRAL taa 723
Contextual Info: WÊ High Performance 256Kxl6 CMOS DRAM AS4C256K16F0 High Speed 256Kxl6 CMOS DRAM Fast Page Mode PRELIMINARY F E A TU R E S 512 refresh cycles, 8 ms refresh interval * Organization: 262,144 words by 16 bits - RAS-only or CAS-before-RAS refresh • High speed

Contextual Info: AS4C256M8D3 2 Gb 256M x 8 bit DDR3 Synchronous DRAM (SDRAM) Confidential Advanced (Rev. 1.0, Feb. /2014) Features Overview • JEDEC Standard Compliant  Power supplies: VDD & VDDQ = +1.5V  0.075V  Operating temperature: - Commercial (0 ~ 95°C)

AS4C256M16D3L

Abstract: 4GB AS4C256M16D3L
Contextual Info: 4Gb DDR3L – AS4C256M16D3L Revision History AS4C256M16D3L - 96-ball FBGA PACKAGE Revision Rev 1.0 Rev 2.0 Details Preliminary datasheet Added "Backward compatible to VDD & VDDQ = 1.5V +/0.075V" - page 2 Added CL=5 & CL=6 to Table 18 – page 31 Updated Table 12. Recommended DC Operating

AS4C256K16FO

Abstract: AS4C256K16FO-60
Contextual Info: AS4C256K16FO 5V 256K X 16 CMOS DRAM Fast Page Mode Features • Organization: 262,144 words x 16 bits • High speed - 25/30/35/50 ns RAS access time - 12/16/18/25 ns column address access time - 7/10/10/10 ns CAS access time • Low power consumption

AS4C256K16E0-50JC

Contextual Info: $6&.  9.ð&026'5$0 ('2 HDWXUHV • Organization: 262,144 words x 16 bits • High speed - 30/35/50 ns RAS access time - 16/18/25 ns column address access time - 7/10/10/10 ns CAS access time • Low power consumption - Active: 500 mW max (AS4C256K16E0-25)

Contextual Info: AS4C256M16D3 Revision History AS4C256M16D3 - 96-ball FBGA PACKAGE Revision Rev 1.0 Rev 2.0 Details Preliminary datasheet Amended temperature range to Table 2. Ordering Information - page 1 - Commercial Extended (0 ~ 95°C) - Industrial (-40 ~ 95°C) Date

Contextual Info: Il High Performance 256Kxl6 CMOS DRAM AS4C256K16F0 High Speed 256Kxl6 CMOS DRAM Fast Page Mode PRELIMINARY I F E A TU R E S_ • 512 refresh cycles, 8 ms refresh interval • Organization: 262,144 words by 16 bits - RAS-only or CAS-before-RAS refresh

Contextual Info: Preliminary information •■ AS4C256K16E0 I I 5V 2 5 6 K X 16 C M O S DRAM EDO Features • O rg a n iz a tio n : 2 6 2 ,1 4 4 w o r d s x 16 b its • 5 1 2 re fre s h c y c le s, 8 m s re fre s h in te rv a l • H ig h sp e e d - R A S -only o r C A S-before-R A S re fre s h o r se lf-re fre sh

AS4C256K16E0

Abstract: AS4C256K16E0-35JC
Contextual Info: AS4C256K16E0 5V 256Kx16 CMOS DRAM EDO Features • Organization: 262,144 words × 16 bits • High speed - 30/35/50 ns RAS access time - 16/18/25 ns column address access time - 7/10/10/10 ns CAS access time • Low power consumption - Active: 500 mW max (AS4C256K16E0-25)

Contextual Info: 4Gb DDR3L – AS4C256M16D3L 256M x 16 bit DDR3L Synchronous DRAM SDRAM Confidential Advanced (Rev. 1.0, April. /2014) Features Overview • JEDEC Standard Compliant  Power supplies: VDD & VDDQ = +1.35V  Operating temperature: - Commercial (0 ~ 95°C)

AS4C256M8D3

Contextual Info: AS4C256M8D3 Revision History AS4C256M8D3 - 78-ball FBGA PACKAGE Revision Rev 1.0 Rev 2.0 Rev 3.0 Details Preliminary datasheet Amended temperature range to Table 2. Ordering information – page 1 - Commercial Extended (0 ~ 95°C) - Industrial (-40 ~ 95°C)

Contextual Info: Preliminary information •■ AS4C256K16F0 II 5V 256KX 16 C M O S DRAM fast page mode Features • Read -modify-write • TTL-compatible, three-state I/O • JEDEC standard packages • Organization: 262,144 words by 16 bits • High speed - 50/60 ns RAS access time

Contextual Info: AS4C256K16E0 5V 256Kx16 CMOS DRAM EDO Features • Organization: 262,144 words × 16 bits • High speed - 30/35/50 ns RAS access time - 16/18/25 ns column address access time - 7/10/10/10 ns CAS access time • Low power consumption - Active: 500 mW max (AS4C256K16E0-25)

Contextual Info: AS4C256M16D3 4Gb 256M x 16 bit DDR3 Synchronous DRAM (SDRAM) Confidential Advanced (Rev. 1.0, Feb. /2014) Features Overview • JEDEC Standard Compliant  Power supplies: VDD & VDDQ = +1.5V  0.075V  Operating temperature: - Commercial (0 ~ 95°C)

G001S

Contextual Info: H igh Perform ance 256K.X 16 CMOS DRAM H AS4C256K16F0 A Hiah Speed 2S6KX16 CMOS DRAM Fast pane mode Preliminary information Features • O rg a n iz a tio n : 2 6 2 ,1 4 4 w o r d s b y 16 b its • R e a d -m o d ify -w rite • H ig h sp e ed - 5 0 /6 0 ns RAS access tim e

Contextual Info: AS4C256K16FO 5V 256K X 16 CMOS DRAM Fast Page Mode Features • Organization: 262,144 words x 16 bits • High speed - 25/30/35/50 ns RAS access time - 12/16/18/25 ns column address access time - 7/10/10/10 ns CAS access time • Low power consumption

AS4C256K16FO-50JC

Contextual Info: AS4C256K16FO 5V 256Kx16 CMOS DRAM fast-page mode Features • Organization: 264,144 words x 16 bits • High speed - 25/30/35/50 ns RAS access time - 12/16/18/25 ns column address access time - 7/10/10/10 ns CAS access time • Low power consumption - Active: 770 mW max (AS4C256K16FO-50)

Contextual Info: AS4C256M8D3 Revision History AS4C256M8D3 - 78-ball FBGA PACKAGE Revision Rev 1.0 Rev 2.0 Details Preliminary datasheet Amended temperature range to Table 2. Ordering Information - page 1 - Commercial Extended (0 ~ 95°C)- Industrial (-40 ~ 95°C) Date February 2014

Contextual Info: 2Gb DDR3L – AS4C256M8D3L 256M x 8 bit DDR3L Synchronous DRAM SDRAM Confidential Advanced (Rev. 1.0, April. /2014) Features Overview • JEDEC Standard Compliant  Power supplies: VDD & VDDQ = +1.35V  Backward compatible to VDD & VDDQ = 1.5V ±0.075V

AS4C256M16D3

Contextual Info: AS4C256M16D3 Revision History AS4C256M16D3 - 96-ball FBGA PACKAGE Revision Rev 1.0 Rev 2.0 Rev 3.0 Details Preliminary datasheet Typo in Table 2 – incorrect part no. page 2 Updated Table 11. Recommended DC Operating Conditions – page 21 Added CL=5 & CL=6 to Table 18 – page 26

as4c256k16eo

Abstract: 256KX16 AS4C256K16E0 LO301
Contextual Info: H ig h P e r fo r m a n c e 256K X 16 CM OS DRAM A S4C 256K 16E 0 A 2 5 6 K X 1 6 CM O S EDO DRAM Preliminary information Features • Extended data out • 512 refresh cycles, 8 ms refresh interval • Organization: 26 2 ,1 4 4 words X 16 bits • High speed

AS4C256K16F0-60JC

Abstract: AS7C164-20PC AS7CI64-20JC AS4LC1M16ES-50TC 120TC 28K1 AS4C1440S 1SPC AS29F040-120TC as7c3
Contextual Info: í U' u i M 11; ! 1Ì ! ! i r 1 ¡ l i ü ’! 4 • -'¡si. í J Mij ! ; , t ‘ i M U I : i Synchronous SRAM part numbering system AS7C X XXXX Voltage: Blin k cram 3 25 18 (X -X X XX = 5V C M O S =3.3V CMOS =2.5V CMOS = 1.8V CMOS Density and organization

6E025

Contextual Info: Features • Refresh • O rganization: 262,144 w o rd s x 16 bits - 512 refresh cycles, 8 ms refresh interval • H ig h speed - 2 5 / 3 0 / 3 5 / 5 0 ns R A S access tim e - RA S-only o r CAS-before-RAS refresh o r self-refresh - 1 2 /1 6 /1 8 /2 5 ns co lu m n address access tim e