el90
Abstract: H352 DL122 DL140 ept20 EPT25 LVEL92 EPT22 H124 ttl databook
Contextual Info: AN1672/D The ECL Translator Guide ECL • TTL • PECL • LVECL • LVPECL • CMOS • LVTTL How To Make Them Talk To Each Other http://onsemi.com Prepared by: Paul Shockman, Paul Hunt ON Semiconductor Logic Applications Engineering APPLICATION NOTE Translation between ECL signals off different power
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H124
Abstract: LVEL17 MC10EPT20
Contextual Info: AN1672/D The ECL Translator Guide PECL • LVPECL • NECL • TTL • LVTTL/LVCMOS • CMOS Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering APPLICATION NOTE Objective This application note is intended to provide the basic device selection and connection information to enable signal
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MC10EPT25
Abstract: MC10EPT22 MC10EPT24 MC10EPT23 MC10EPT21 ttl 7709 AND8072 HCT CMOS family characteristics AN1568 AND8020
Contextual Info: AN1672/D The ECL Translator Guide PECL • LVPECL • NECL • TTL • LVTTL/LVCMOS • CMOS http://onsemi.com Prepared by: Paul Shockman ON Semiconductor APPLICATION NOTE Objective receiver in the LOW state. In contrast, ECL drivers source current in both HIGH and LOW states to the receiver).
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EL90
Abstract: AN1568 AND8020 AND8066 AND8072 MC10EP195 H124 MC10EPT22 MC10EPT20
Contextual Info: AN1672/D The ECL Translator Guide PECL • LVPECL • NECL • TTL • LVTTL/LVCMOS • CMOS http://onsemi.com Prepared by: Paul Shockman ON Semiconductor APPLICATION NOTE Objective This application note is intended to provide the basic device selection and connection information to enable signal
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ELT24
Abstract: AN1568 AND8020 AND8066 AND8072 MC10EP195 H124 MC10EPT22 MC10EPT20
Contextual Info: AN1672/D The ECL Translator Guide PECL • LVPECL • NECL • TTL • LVTTL/LVCMOS • CMOS http://onsemi.com Prepared by: Paul Shockman ON Semiconductor APPLICATION NOTE Objective This application note is intended to provide the basic device selection and connection information to enable signal
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100EL91
Abstract: MC100EL91 MC100EL91DW MC100EL91DWR2 MC100LVEL91
Contextual Info: MC100EL91 3.3V / 5VĄTriple LVPECL / PECL Input to -5V ECL Output Translator The MC100EL91 is a triple LVPECL / PECL input to ECL output translator. The device receives standard or low voltage differential PECL signals, determined by the VCC supply level, and translates them
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E212 transistor
Abstract: E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2 D200-400
Contextual Info: MC10E112, MC100E112 5VĄECL Quad Driver The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock
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AND8020
Abstract: EL90 MC100EL90 MC100EL90DW MC100EL90DWR2 100EL90
Contextual Info: MC100EL90 -3.3V / -5VĄTriple ECL Input to PECL Output Translator The MC100EL90 is a triple ECL to PECL translator. The device receives either –3.3 V or –5 V differential ECL signals, determined by the VEE supply level, and translates them to standard +5 V differential PECL
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KPT25
Abstract: EPT25 MC100EPT25 MC100EPT25D MC100EPT25DR2 MC100EPT25DT MC100EPT25DTR2 KA25 kpt25 alyw
Contextual Info: MC100EPT25 −3.3V / −5V Differential ECL to +3.3V LVTTL Translator The MC100EPT25 is a Differential ECL to LVTTL translator. This device requires +3.3 V, -3.3 V to -5.2 V, and ground. The small outline 8-lead package and the single gate of the EPT25 make it ideal
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LQFP32
Abstract: LQFP-32 MC100 MC100EPT622 MC100EPT622FA MC100EPT622FAR2
Contextual Info: MC100EPT622 3.3V LVTTL/LVCMOS to LVPECL Translator The MC100EPT622 is a 10- Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The device has an OR- ed enable input which can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs
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marking CODE D2B
Abstract: MC100E104 MC100E104FN MC100E104FNR2 MC10E104 MC10E104FN MC10E104FNR2 marking D3B ECL IC NAND
Contextual Info: MC10E104, MC100E104 5VĄECL Quint 2ĆInput AND/NAND Gate The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be
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KVT23
Abstract: MC100LVELT23 MC100LVELT23D MC100LVELT23DR2 MC100LVELT23DT
Contextual Info: MC100LVELT23 3.3V Dual Differential LVPECL to LVTTL Translator The MC100LVELT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The small outline 8-lead package and the dual gate design of the LVELT23 makes it ideal for applications which
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MC100EP90
Abstract: MC100EP90DT MC100EP90DTR2 MC10EP90 MC10EP90DT MC10EP90DTR2
Contextual Info: MC10EP90, MC100EP90 -3.3V / -5VĄTriple ECL Input to LVPECL/PECL Output Translator The MC10/100EP90 is a TRIPLE ECL TO LVPECL/PECL translator. The device receives differential LVECL or ECL signals and translates them to differential LVPECL or PECL output signals.
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MC100E116
Abstract: MC100E116FN MC100E116FNR2 MC10E116 MC10E116FN MC10E116FNR2 E116
Contextual Info: MC10E116, MC100E116 5VĄECL Quint Differential Line Receiver The MC10E/100E116 is a quint differential line receiver with emitter-follower outputs. For applications which require bandwidths greater than that of the E116, the E416 device may be of interest.
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KEL04
Abstract: HL04 HEL04 e104 MC100EL04 MC10EL04 HL-04
Contextual Info: MC10EL04, MC100EL04 5VĄECL 2ĆInput AND/NAND The MC10EL/100EL04 is a 2-input AND/NAND gate. The device is functionally equivalent to the E104 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E104, the EL04 is ideally suited for those
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N100
Abstract: NB100LVEP17 NB100LVEP17DT NB100LVEP17DTR2 NB100LVEP17MN TSSOP-20 qfn24 socket N100 transistor QFN-24
Contextual Info: NB100LVEP17 2.5V / 3.3V / 5V ECL Quad Differential Driver/Receiver The NB100LVEP17 is a 4-bit differential line receiver. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications.
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KEP05
Abstract: HEP05 MC100EP05 MC10EP05
Contextual Info: MC10EP05, MC100EP05 3.3V / 5VĄECL 2-Input Differential AND/NAND The MC10/100EP05 is a 2–input differential AND/NAND gate. The device is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP05 is ideal for applications requiring the fastest AC performance
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EP809
Abstract: MC100EP809 MC100EP809FA MC100EP809FAG MC100 SY89809L MC100EP809FAR2 MC100EP809FAR2G
Contextual Info: MC100EP809 3.3V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable http://onsemi.com Description The MC100EP809 is a low skew 1−to−9 differential clock driver, designed with clock distribution in mind, accepting two clock sources into
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100EL91
Abstract: MC100EL91 MC100LVEL91
Contextual Info: MC100EL91 5 V Triple PECL Input to −5 V ECL Output Translator Description The MC100EL91 is a triple PECL input to ECL output translator. The device receives standard voltage differential PECL signals, determined by the VCC supply level, and translates them to differential
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KVL11
Abstract: KV11 LVEL11 MC100LVEL11
Contextual Info: MC100LVEL11 3.3V ECL 1:2 Differential Fanout Buffer Description The MC100LVEL11 is a differential 1:2 fanout buffer. The device is functionally similar to the E111 device but with higher performance capabilities. Having within-device skews and output transition times
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EP29
Abstract: MC100EP29 MC10EP29
Contextual Info: MC10EP29, MC100EP29 3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset http://onsemi.com Description The MC10/100EP29 is a dual master−slave flip−flop. The device features fully differential Data and Clock inputs as well as outputs.
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KV05
Abstract: KVL05 MC100EL05 MC100LVEL05 MC100LVEL05MNR4G
Contextual Info: MC100LVEL05 3.3V ECL 2-Input Differential AND/NAND Description The MC100LVEL05 is a 2-input differential AND/NAND gate. The device is functionally equivalent to the MC100EL05 device and operates from a 3.3 V supply voltage. With propagation delays and output transition times equivalent to the EL05, the LVEL05 is ideally
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MC100E416
Abstract: MC10E416 MC10E416FN
Contextual Info: MC10E416, MC100E416 5V ECL Quint Differential Line Receiver Description The MC10E416/100E416 is a 5-bit differential line receiving device. The 2.0 GHz of bandwidth provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators.
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405C
Abstract: 485G NB6L239
Contextual Info: NB6L239 2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider http://onsemi.com Description The NB6L239 is a high−speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; B1/2/4/8
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