100EL91
Abstract: MC100EL91 MC100EL91DW MC100EL91DWR2 MC100LVEL91
Contextual Info: MC100EL91 3.3V / 5VĄTriple LVPECL / PECL Input to -5V ECL Output Translator The MC100EL91 is a triple LVPECL / PECL input to ECL output translator. The device receives standard or low voltage differential PECL signals, determined by the VCC supply level, and translates them
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MC100EL91
MC100EL91
MC100LVEL91.
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MC100EL91/D
100EL91
MC100EL91DW
MC100EL91DWR2
MC100LVEL91
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E212 transistor
Abstract: E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2 D200-400
Contextual Info: MC10E112, MC100E112 5VĄECL Quad Driver The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock
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MC10E112,
MC100E112
MC10E/100E112
MC10E/100E111
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MC10E112/D
E212 transistor
E112
E212
MC100E112
MC100E112FN
MC10E112
MC10E112FN
MC10E112FNR2
D200-400
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AND8020
Abstract: EL90 MC100EL90 MC100EL90DW MC100EL90DWR2 100EL90
Contextual Info: MC100EL90 -3.3V / -5VĄTriple ECL Input to PECL Output Translator The MC100EL90 is a triple ECL to PECL translator. The device receives either –3.3 V or –5 V differential ECL signals, determined by the VEE supply level, and translates them to standard +5 V differential PECL
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MC100EL90
MC100EL90
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MC100EL90/D
AND8020
EL90
MC100EL90DW
MC100EL90DWR2
100EL90
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KPT25
Abstract: EPT25 MC100EPT25 MC100EPT25D MC100EPT25DR2 MC100EPT25DT MC100EPT25DTR2 KA25 kpt25 alyw
Contextual Info: MC100EPT25 −3.3V / −5V Differential ECL to +3.3V LVTTL Translator The MC100EPT25 is a Differential ECL to LVTTL translator. This device requires +3.3 V, -3.3 V to -5.2 V, and ground. The small outline 8-lead package and the single gate of the EPT25 make it ideal
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MC100EPT25
MC100EPT25
EPT25
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MC100EPT25/D
KPT25
MC100EPT25D
MC100EPT25DR2
MC100EPT25DT
MC100EPT25DTR2
KA25
kpt25 alyw
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marking CODE D2B
Abstract: MC100E104 MC100E104FN MC100E104FNR2 MC10E104 MC10E104FN MC10E104FNR2 marking D3B ECL IC NAND
Contextual Info: MC10E104, MC100E104 5VĄECL Quint 2ĆInput AND/NAND Gate The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be
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MC10E104,
MC100E104
MC10E/100E104
MC10E104FN
EIA/JESD78
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MC10E104/D
marking CODE D2B
MC100E104
MC100E104FN
MC100E104FNR2
MC10E104
MC10E104FN
MC10E104FNR2
marking D3B
ECL IC NAND
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KVT23
Abstract: MC100LVELT23 MC100LVELT23D MC100LVELT23DR2 MC100LVELT23DT
Contextual Info: MC100LVELT23 3.3V Dual Differential LVPECL to LVTTL Translator The MC100LVELT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The small outline 8-lead package and the dual gate design of the LVELT23 makes it ideal for applications which
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MC100LVELT23
MC100LVELT23
LVELT23
MC100LVELT23/D
KVT23
MC100LVELT23D
MC100LVELT23DR2
MC100LVELT23DT
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MC100E116
Abstract: MC100E116FN MC100E116FNR2 MC10E116 MC10E116FN MC10E116FNR2 E116
Contextual Info: MC10E116, MC100E116 5VĄECL Quint Differential Line Receiver The MC10E/100E116 is a quint differential line receiver with emitter-follower outputs. For applications which require bandwidths greater than that of the E116, the E416 device may be of interest.
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MC10E116,
MC100E116
MC10E/100E116
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MC10E116/D
MC100E116
MC100E116FN
MC100E116FNR2
MC10E116
MC10E116FN
MC10E116FNR2
E116
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MC100LVEL01
Abstract: MC100LVEL01D 1085 SPICE model
Contextual Info: MC100LVEL01 3.3VĄECL 4-Input OR/NOR The MC100LVEL01 is a 4–input OR/NOR gate. The device is functionally equivalent to the EL01 device and works from a 3.3 V supply. With AC performance similar to the EL01 device, the LVEL01 is ideal for low voltage applications which require the ultimate in
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MC100LVEL01
MC100LVEL01
LVEL01
KVL01
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MC100LVEL01/D
MC100LVEL01D
1085 SPICE model
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KEL04
Abstract: HL04 HEL04 e104 MC100EL04 MC10EL04 HL-04
Contextual Info: MC10EL04, MC100EL04 5VĄECL 2ĆInput AND/NAND The MC10EL/100EL04 is a 2-input AND/NAND gate. The device is functionally equivalent to the E104 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E104, the EL04 is ideally suited for those
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MC10EL04,
MC100EL04
MC10EL/100EL04
AND8003/D
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KEL04
HL04
HEL04
e104
MC100EL04
MC10EL04
HL-04
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IC CD 4030 pin configuration
Abstract: MC34182D E197 MC10E197 MC10E197FN MC10E197FNR2 root locus applications
Contextual Info: MC10E197 5V ECL Data Separator The MC10E197 is an integrated data separator designed for use in high speed hard disk drive applications. With data rate capabilities of up to 50 Mb/s the device is ideally suited for today’s and future state-of-the-art hard disk designs.
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MC10E197
MC10E197
MC10E197/D
IC CD 4030 pin configuration
MC34182D
E197
MC10E197FN
MC10E197FNR2
root locus applications
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MC100E163
Abstract: MC100E163FN MC100E163FNR2 MC10E163 MC10E163FN MC10E163FNR2
Contextual Info: MC10E163, MC100E163 5VĄECL 2ĆBit 8:1 Multiplexer The MC10E/100E163 contains two 8:1 multiplexers with differential outputs and common select inputs. The select inputs SEL0, 1, 2 control which one of the eight data inputs (A0 – A7, B0 – B7) is propagated to the output.
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MC10E163,
MC100E163
MC10E/100E163
MC10E163FN
EIA/JESD78
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MC10E163/D
MC100E163
MC100E163FN
MC100E163FNR2
MC10E163
MC10E163FN
MC10E163FNR2
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MC100EL59
Abstract: MC100EL59DW MC100EL59DWR2 AND8020
Contextual Info: MC100EL59 5VĄECL Triple 2:1 Multiplexer The MC100EL59 is a triple 2:1 multiplexer with differential outputs. The output data of the multiplexers can be controlled individually via the select inputs or as a group via the common select input. The flexible selection scheme makes the device useful for both data path and random
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MC100EL59
MC100EL59
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MC100EL59/D
MC100EL59DW
MC100EL59DWR2
AND8020
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E211
Abstract: MC100E211 MC100E211FN MC100E211FNR2 MC10E211 MC10E211FN MC10E211FNR2 marking code 2b
Contextual Info: MC10E211, MC100E211 5VĄECL 1:6 Differential Clock Distribution Chip The MC10E/100E211 is a low skew 1:6 fanout device designed explicitly for low skew clock distribution applications. The E211 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed
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MC10E211,
MC100E211
MC10E/100E211
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MC10E211/D
E211
MC100E211
MC100E211FN
MC100E211FNR2
MC10E211
MC10E211FN
MC10E211FNR2
marking code 2b
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MC100E154
Abstract: MC100E154FN MC100E154FNR2 MC10E154 MC10E154FN MC10E154FNR2
Contextual Info: MC10E154, MC100E154 5VĄECL 5ĆBit 2:1 MuxĆLatch The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on
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MC10E154,
MC100E154
MC10E/100E154
MC10E154FN
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MC10E154/D
MC100E154
MC100E154FN
MC100E154FNR2
MC10E154
MC10E154FN
MC10E154FNR2
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EL12
Abstract: MC100LVEL12 MC100LVEL12D
Contextual Info: MC100LVEL12 3.3VĄECL Low Impedance Driver The MC100LVEL12 is a low impedance drive buffer. With two pairs of OR/NOR outputs the device is ideally suited for high drive applications such as memory addressing. The device is functionally equivalent to the EL12 device and operates from a 3.3 V power supply.
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MC100LVEL12
MC100LVEL12
LVEL12
KVL12it
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EL12
MC100LVEL12D
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transistor BD 889
Abstract: MC10E1651 MC10E1651FN MC10E1651FNR2 MC10E1651L
Contextual Info: MC10E1651 5V, -5VĄECL Dual ECL Output Comparator with Latch The MC10E1651 is fabricated using ON Semiconductor’s advanced MOSAIC IIIt process. The MC10E1651 incorporates a fixed level of input hysteresis as well as output compatibility with 10 KH logic
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MC10E1651
MC10E1651
16-pin
20-pin
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transistor BD 889
MC10E1651FN
MC10E1651FNR2
MC10E1651L
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100EL56
Abstract: MC100EL56 MC100EL56DW MC100EL56DWR2
Contextual Info: MC100EL56 5V ECL Dual Differential 2:1 Multiplexer The MC100EL56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. Multiple VBB pins are provided to ease AC coupling input signals.
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MC100EL56
MC100EL56
MC100EL56/D
100EL56
MC100EL56DW
MC100EL56DWR2
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E112
Abstract: E212 MC100E212 MC100E212FN MC100E212FNR2 MC10E212 MC10E212FN MC10E212FNR2 E212 transistor
Contextual Info: MC10E212, MC100E212 5VĄECL 3ĆBit Scannable Registered Address Driver The MC10E/100E212 is a scannable registered ECL driver typically used as a fan-out memory address driver for ECL cache driving. In a VLSI array based CPU design, use of the E212 allows the user to
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MC10E212,
MC100E212
MC10E/100E212
MC10E212FN
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MC10E212/D
E112
E212
MC100E212
MC100E212FN
MC100E212FNR2
MC10E212
MC10E212FN
MC10E212FNR2
E212 transistor
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MC100E157
Abstract: MC100E157FN MC100E157FNR2 MC10E157 MC10E157FN MC10E157FNR2
Contextual Info: MC10E157, MC100E157 5VĄECL Quad 2:1 Multiplexer The MC10E/100E157 contains four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select SEL inputs. The individual select control makes the devices well suited for random logic designs.
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MC10E157,
MC100E157
MC10E/100E157
MC10E157FN
EIA/JESD78
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MC10E158/D
MC100E157
MC100E157FN
MC100E157FNR2
MC10E157
MC10E157FN
MC10E157FNR2
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KVL33
Abstract: EL33 MC100LVEL33 MC100LVEL33D
Contextual Info: MC100LVEL33 3.3VĄECL ÷4 Divider The MC100LVEL33 is an integrated ÷4 divider. The LVEL is functionally equivalent to the EL33 and works from a 3.3 V supply. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the
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MC100LVEL33
MC100LVEL33
LVEL33
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KVL33
EL33
MC100LVEL33D
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E431
Abstract: MC100E431 MC100E431FN MC100E431FNR2 MC10E431 MC10E431FN MC10E431FNR2
Contextual Info: MC10E431, MC100E431 5VĄECL 3ĆBit Differential FlipĆFlop The MC10E/100E431 is a 3-bit flip-flop with differential clock, data input and data output. The asynchronous Set and Reset controls are edge-triggered rather than level controlled. This allows the user to rapidly set or reset the
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MC10E431,
MC100E431
MC10E/100E431
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MC10E431/D
E431
MC100E431
MC100E431FN
MC100E431FNR2
MC10E431
MC10E431FN
MC10E431FNR2
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LVE222
Abstract: MC100LVE222 MC100LVE222FA MC100LVE222FAR2 MB113
Contextual Info: MC100LVE222 3.3 V ECL 1:15 Differential ÷1/÷2 Clock Driver The MC100LVE222 is a low skew 1:15 differential ÷1/÷2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be differential or used single- ended with VBB output reference bypassed and connected to the
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MC100LVE222
MC100LVE222
LVE222
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MC100LVE222/D
MC100LVE222FA
MC100LVE222FAR2
MB113
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MC100EPT24
Abstract: MC100EPT24D MC100EPT24DR2 MC100EPT24DT MC100EPT24DTR2 ka24
Contextual Info: MC100EPT24 3.3VĄLVTTL/LVCMOS to Differential LVECL Translator The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL translator. Because LVECL levels and LVTTL/LVCMOS levels are used, a –3.3 V, +3.3 V and ground are required. The small outline 8–lead package and the single gate of the EPT24 makes it ideal for
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MC100EPT24
MC100EPT24
EPT24
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MC100EPT24/D
MC100EPT24D
MC100EPT24DR2
MC100EPT24DT
MC100EPT24DTR2
ka24
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HEL89
Abstract: MC10EL89 MC10EL89D MC10EL89DR2 MC10EL89DT MC10EL89DTR2 IC D 3555 PS
Contextual Info: MC10EL89 5V ECL Coaxial Cable Driver The MC10EL89 is a differential fanout gate specifically designed to drive coaxial cables. The device is especially useful in Digital Video Broadcasting applications; for this application, since the system is polarity free, each output can be used as an independent driver. The
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MC10EL89
MC10EL89
MC10EL89/D
HEL89
MC10EL89D
MC10EL89DR2
MC10EL89DT
MC10EL89DTR2
IC D 3555 PS
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