AN156 Search Results

EP809

Abstract: AN1406 EP14 P1596 LVEL16 MC100ELxx AN1568
Contextual Info: AN1568/D Interfacing Between LVDS and ECL Prepared by: Paul Shockman Logic Applications Engineering http://onsemi.com APPLICATION NOTE LVDS outputs require a 100 Ω load between the differential outputs. This load will in addition terminate the 50 Ω controlled impedance lines.

kvg crystal FILTER XF9-B

Abstract: XF-9B 2f3 transistor SL6440 Broadband Amplifiers Application Notes WESCOn mixer Broadband Amplifiers Application Notes, appendix 3 KVG filters vmos fet plessey sl6440
Contextual Info: AN156 Intermodulation, Phase Noise and Dynamic Range AN156 - 3.2 September 1993 The radio receiver operates in a non-benign environment. It needs to pick out a very weak wanted signal from a background of noise at the same time as it rejects a large number to much stronger unwanted signals. These may be

"laser diode Driver Circuit"

Abstract: AN137 AN140 AN156 X9520 X9530 cccs "network interface cards"
Contextual Info: Application Note AN156 Using the X9530 in Fiber Optic Applications By Joe Ciancio 1 INTRODUCTION Fiber optics are used more and more everyday in the areas of telecommunications, and data networks. Transmitter boards used in such networks as SONET and SDH, commonly use fiber optics to provide high

AN1560

Abstract: DK3200 abel i2c DK3200 Evaluation Board C51 Family uPSD3200 lm339 pwm speed 8032 intel AGILENT H2000 MON51
Contextual Info: AN1560 APPLICATION NOTE Design Guide µPSD3200 Family MPCONTENTS • µPSD3200 Family Overview ■ DK3200 Overview ■ DK3200 Development Board ■ Entering Design in PSDsoft Express ■ Watch it Run on DK3200 ■ Using uVision2 and ISD51 Debugger from Keil

Contextual Info: NB100LVEP222 2.5 V/3.3 V 1:15 Differential ECL/PECL ÷1/÷2 Clock Driver The NB100LVEP222 is a low skew 1:15 differential ÷1/÷2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be used in a differential

Contextual Info: MC10EP142, MC100EP142 3.3V / 5VĄECL 9-Bit Shift Register The MC10EP/100EP142 is a 9–bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs

KPT22

Contextual Info: MC100EPT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator Description The MC100EPT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The small outline 8−lead

klt22

Abstract: HLT22 ELT22 HT22 MC100 MC100ELT22 MC10ELT22
Contextual Info: MC10ELT22, MC100ELT22 5V Dual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL Positive ECL levels are used only +5 V and ground are required. The small outline 8-lead package and the low

1277n

Abstract: D1175 100P6S-A M30833FJGP M30833MJGP M30835FJGP M30835MJGP sis8 SIS11 transistor sr50
Contextual Info: n r de me Un elop v de t Preliminary Specifications REV.B1 Mitsubishi Microcomputers M32C/83 group Specifications in this manual are tentative and subject to change. Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER About M32C/83 Group The M32C/83 group of single-chip microcomputers are built using a high-performance silicon gate CMOS

KVL05

Abstract: ECL IC NAND KV05 MC100EL05 MC100LVEL05 ecl nand Logic Family Specifications
Contextual Info: MC100LVEL05 3.3VĄECL 2ĆInput Differential AND/NAND The MC100LVEL05 is a 2-input differential AND/NAND gate. The device is functionally equivalent to the MC100EL05 device and operates from a 3.3 V supply voltage. With propagation delays and output transition times equivalent to the EL05, the LVEL05 is ideally

KEP16

Abstract: LVEL16 MC100EP16 MC10EP16
Contextual Info: MC10EP16, MC100EP16 3.3V / 5VĄECL Differential Receiver/Driver The EP16 is a world–class differential receiver/driver. The device is functionally equivalent to the EL16 and LVEL16 devices with higher performance capabilities. With output transition times significantly

KLT21

Abstract: HLT21 ELT21 HT21 MC100ELT21 MC10ELT21 MC10ELT21DR2
Contextual Info: MC10ELT21, MC100ELT21 5V Differential PECL to TTL Translator The MC10ELT/100ELT21 is a differential PECL to TTL translator. Because PECL Positive ECL levels are used, only +5 V and ground are required. The small outline 8-lead package and the single gate of

100EL90

Abstract: EL90 MC100EL90 MC100EL90DW
Contextual Info: MC100EL90 −3.3V / −5V Triple ECL Input to PECL Output Translator Description The MC100EL90 is a triple ECL to PECL translator. The device receives either −3.3 V or −5 V differential ECL signals, determined by the VEE supply level, and translates them to standard +5 V differential

MC100E122

Abstract: MC10E122 MC10E122FN MC10E122FNG
Contextual Info: MC10E122, MC100E122 5V ECL 9-Bit Buffer Description The MC10E/100E122 is a 9-bit buffer. The device contains nine non-inverting buffer gates. The 100 Series contains temperature compensation. http://onsemi.com Features • 500 ps Max. Propagation Delay • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V

MC100EL13

Abstract: MC100EL13DW
Contextual Info: MC100EL13 5V ECL Dual 1:3 Fanout Buffer The MC100EL13 is a dual, fully differential 1:3 fanout buffer. The Low Output−Output Skew of the device makes it ideal for distributing two different frequency synchronous signals. The differential inputs have special circuitry which ensures device

MC100LVEL39

Abstract: MC100LVEL39DW
Contextual Info: MC100LVEL39 3.3V ECL ÷2/4, ÷4/6 Clock Generation Chip Description The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common

EP11

Abstract: LVEL11 NB6L11 NB6L11DG NB6L11DR2G
Contextual Info: NB6L11 2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator The NB6L11 is an enhanced differential 1:2 clock or data fanout buffer/translator. The device has the same pinout and is functionally equivalent to the LVEL11, EP11, LVEP11 devices. Moreover, the

MC10E111

Abstract: MC10E411 MC10E411FN MC10E411FNG
Contextual Info: MC10E411 5V ECL 1:9 Differential PECL/NECL RAMBus Clock Buffer Description The MC10E411 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The MC10E411’s function and performance are similar to the popular MC10E111, with the added

MC100LVEL30

Abstract: MC100LVEL30DW
Contextual Info: MC100LVEL30 3.3V ECL Triple D Flip−Flop with Set and Reset Description The MC100LVEL30 is a triple master−slave D flip−flop with differential outputs. Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the

MC100EP52

Abstract: HEP52 KEP52 MC100 MC10EP52
Contextual Info: MC10EP52, MC100EP52 3.3V / 5V ECL Differential Data and Clock D Flip−Flop Description The MC10EP/100EP52 is a differential data, differential clock D flip−flop. The device is pin and functionally equivalent to the EL52 device. Data enters the master portion of the flip−flop when the clock is

100E195

Abstract: E195 MC100E195 MC10E195
Contextual Info: MC10E195, MC100E195 5V ECL Programmable Delay Chip Description The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in

MC100E457

Abstract: MC10E457 MC10E457FN LM 374 ic configuration
Contextual Info: MC10E457, MC100E457 5V ECL Triple Differential 2:1 Multiplexer Description The MC10E457/100E457 is a 3-bit differential 2:1 multiplexer. The fully differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals.

100EL56

Abstract: MC100EL56 MC100EL56DW
Contextual Info: MC100EL56 5V ECL Dual Differential 2:1 Multiplexer Description The MC100EL56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. Multiple VBB pins are

100LVEL40

Abstract: MC100LVEL40 MC10LVEL40DW
Contextual Info: MC100LVEL40 3.3/5V ECL Differential Phase−Frequency Detector Description The MC100LVEL40 is a three state phase frequency−detector intended for phase−locked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design