AD 149 AE9
Abstract: AA23 PQ208 QL3040 QL3040-1PB456C QL3040-1PQ208C
Contextual Info: QL3040 pASIC 3 FPGA Data Sheet •••••• 40,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • 40,000 Usable PLD Gates with 252 I/Os • 300 MHz 16-bit Counters, 400 MHz Datapaths
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ql304016-bitad 149 ae9aa23+3pq208ql3040-1pb456cql3040-1pq208c
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AE21 ARRAY DIODE
Abstract: QL3060 AD 149 AE9 AA23 PQ208 QL3060-1PB456C QL3060-1PQ208C B14 ON
Contextual Info: QL3060 pASIC 3 FPGA Data Sheet •••••• 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • 60,000 Usable PLD Gates with 316 I/Os • 300 MHz 16-bit Counters, 400 MHz Datapaths
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ql306016-bitae21 array diodead 149 ae9+5aa23pq208ql3060-1pb456cql3060-1pq208cb14 on
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diodes t25 4 l9
Abstract: EPF10K30AB356 EPF10K200E
Contextual Info: FLEX 10KE Embedded Programmable Logic Family August 1998, ver. 1 Features. Data Sheet • Preliminary Information ■ ■ ■ Embedded programmable logic device PLD family, providing system integration in a single device – Enhanced embedded array for implementing megafunctions
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16-bitdiodes t25 4 l9epf10k30ab356epf10k200e |
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lcmx01200c
Abstract: smd m21 sot23 fuse smd marking f5 marking w25 SMD smd diode U12 c526 LCMXO1200C-CSBGA132 npn transistor smd w19 transistor C535 SMD BGA 672 DRAWING SPI-M2564
Contextual Info: LatticeECP2M PCI Express Solutions Board User’s Guide September 2008 Revision: EB33_01.0 LatticeECP2M PCI Express Solutions Board User’s Guide Lattice Semiconductor Introduction As PCI Express applications have emerged, the LatticeECP2M FPGA family has become a well-suited solution
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cy2304sc-1cts-cb3lv-3c10000mhzcb3lv-3c-100m0000-t+15exb2hv471jv33r-0603smterj-3ekf33r0v1/16w1m-0603smtlcmx01200csmd m21 sot23fuse smd marking f5marking w25 smdsmd diode u12 c526lcmxo1200c-csbga132npn transistor smd w19transistor c535smd bga 672 drawingspi-m2564
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PQ208
Abstract: PQ240 QL4058 QL4058-1PB456C QL4058-1PQ208C QL4058-1PQ240C aldec g2
Contextual Info: QL4058 QuickRAM Data Sheet • • • • • • 58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM Device Highlights Advanced I/O Capabilities • Interfaces with both 3.3 V and 5.0 V devices High Performance & High Density
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ql405816-bitpq208pq240+4ql4058-1pb456cql4058-1pq208cql4058-1pq240caldec g2
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AD 149 AE9
Abstract: PQ208 PQ240 QL4090 QL4090-1PB456C QL4090-1PQ208C QL4090-1PQ240C aldec g2 CQFP 240
Contextual Info: QL4090 QuickRAM Data Sheet • • • • • • 90,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM Device Highlights Advanced I/O Capabilities • Interfaces with both 3.3 V and 5.0 V devices High Performance & High Density
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ql409016-bitad 149 ae9pq208+6pq240ql4090-1pb456cql4090-1pq208cql4090-1pq240caldec g2cqfp 240
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diode t25 4 k8
Abstract: diode t25 4 B9 diode t25 4 H9 diode t25 4 k5 diode t25 4 L9 diode AA17 diode t25 4 k6 diode t25 4 g8 diode t25 4 G9 T4 w4 DIODE
Contextual Info: Pin Information For The Stratix EP1S10 Device, ver 3.1 Bank Number B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B1 B1 VREF Bank Pin Name/Function Optional Function s
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ep1s10diode t25 4 k8diode t25 4 b9diode t25 4 h9+7diode t25 4 k5diode t25 4 l9diode aa17diode t25 4 k6diode t25 4 g8diode t25 4 g9t4 w4 diode
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altera an33 configuring FLEX 8000
Contextual Info: FLEX 10KE Embedded Programmable Logic Family November 1998. ver. 1.01 Features. Data Sheet • Preliminary Information ■ ■ ■ Em bedded program m able logic device PLD family, providing system integration in a single device Enhanced em bedded array for im plem enting megafunctions
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16-bit256-pinepf10k30eepf10k50e+7epf10k100b672-pinepf10k100e484-pinepf10k130eepf10k200ealtera an33 configuring flex 8000
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diode AB26
Abstract: F17 DIODE AF12 diode
Contextual Info: Pin Information For The Stratix EP1S25 Device, ver 3.0 Bank Number B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREF Bank Pin Name/Function Optional Function s VREF0B2 VREF0B2 VREF0B2 VREF0B2
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ep1s25rx38prx38ntx38p+9tx38nrx37prx37ntx37ptx37nrx36pdiode ab26f17 diodeaf12 diode
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diode t25 4 H9
Abstract: diode t25 4 B8 diode t25 4 G9 diode t25 4 k6 diode t25 4 H8 diode t25 4 F8 diode t25 4 e9 diode t25 4 e8 diode t25 4 g8 diode t25 4 L9
Contextual Info: Pin Information For The Stratix EP1S25 Device, ver 3.6 Bank Number B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2
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ep1s25pt-ep1s25-3diode t25 4 h9diode t25 4 b8+8diode t25 4 g9diode t25 4 k6diode t25 4 h8diode t25 4 f8diode t25 4 e9diode t25 4 e8diode t25 4 g8diode t25 4 l9
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diode t25 4 H9
Abstract: diode t25 4 L9 diode t25 4 k6 diode t25 4 k8 diode t25 4 G9 diode t25 4 F8 diode t25 4 B9 diode t25 4 g8 diode t25 4 F7 diode t25 4 L8
Contextual Info: Pin Information For The Stratix EP1S10 Device, ver 3.7 Note 2 Bank Number B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B1 B1 B1 B1 B1 B1 B1 B1 B1
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ep1s10pt-ep1s10-3ep1s10f484diode t25 4 h9+9diode t25 4 l9diode t25 4 k6diode t25 4 k8diode t25 4 g9diode t25 4 f8diode t25 4 b9diode t25 4 g8diode t25 4 f7diode t25 4 l8
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diode t25 4 g8
Abstract: diode AA19 diode t25 4 H9 diode AA16 T4 w4 DIODE diode t25 4 G9 DSAUTAZ001023.txt diode t25 4 k8 Diode D25 N12 diode v6 N9
Contextual Info: Pin Information For The Stratix EP1S20 Device, ver 3.0 Bank Number B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREF Bank Pin Name/Function Optional Function s VREF0B2 VREF0B2 VREF0B2 VREF0B2
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ep1s20rx32prx32ntx32p+16tx32nrx31prx31ntx31ptx31nrx30pdiode t25 4 g8diode aa19diode t25 4 h9diode aa16t4 w4 diodediode t25 4 g9dsautaz001023.txtdiode t25 4 k8diode d25 n12diode v6 n9
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Contextual Info: BACK Accelerator Series FPGAs – ACT 3 PCI-Compliant Family Features • Up to 10,000 Gate Array Equivalent Gates. • Up to 250 MHz On-Chip Performance. • 9.0 ns Clock-to-Output. • Up to 1,153 Dedicated Flip-Flops. • Up to 228 User-Programmable I/O Pins.
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ACT 3 Accelerator
Abstract: ACT 3 accelerator FPGAs Actel Accelerator fpga datasheet DLM8 A1425A-3
Contextual Info: Accelerator Series FPGAs – ACT 3 PCI-Compliant Family Features • Up to 10,000 Gate Array Equivalent Gates. • Up to 250 MHz On-Chip Performance. • 9.0 ns Clock-to-Output. • Up to 1,153 Dedicated Flip-Flops. • Up to 228 User-Programmable I/O Pins.
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a1460bpa14100bpact 3 acceleratoract 3 accelerator fpgas+3actel accelerator fpga datasheetdlm8a1425a-3
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Diode D25 N12
Abstract: diode t25 4 H9 DIODE T25 4 H5 diode t25 4 G9 diode t25 4 k6 diode t25 4 g8 diode AA17 diode t25 4 F7 diode t25 4 k8 diode AB26
Contextual Info: Pin Information For The Stratix EP1S10 Device, ver 3.0 Bank Number B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREF Bank Pin Name/Function Optional Function s VREF0B2 VREF0B2 VREF0B2
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ep1s10rx21prx21ntx21p+11tx21ndiode d25 n12diode t25 4 h9diode t25 4 h5diode t25 4 g9diode t25 4 k6diode t25 4 g8diode aa17diode t25 4 f7diode t25 4 k8diode ab26
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diode t25 4 k8
Abstract: diode t25 4 L9 diode t25 4 g8 diode t25 4 G9 diode t25 4 k6 diode t25 4 B9 Diode D25 N12 diode t25 4 d7 diode t25 4 j6 diode t25 4 F6
Contextual Info: Pin Information For The Stratix EP1S20 Device, ver 3.1 Bank Number B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2
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ep1s20diode t25 4 k8diode t25 4 l9diode t25 4 g8+7diode t25 4 g9diode t25 4 k6diode t25 4 b9diode d25 n12diode t25 4 d7diode t25 4 j6diode t25 4 f6
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A1425A-3
Contextual Info: ACT3PCI.fm v6 Page 1 Tuesday, August 12, 1997 11:17 AM Accelerator Series FPGAs: ACT 3 PCI-Compliant Family F e atures • Up to 10,000 Gate Array Equivalent Gates. • Up to 250 MHz On-Chip Performance. • 9.0 ns Clock-to-Output. • Up to 1,153 Dedicated Flip-Flops.
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rd8 f01 ad
Abstract: MOCK
Contextual Info: Æ k ù iil Accelerator Series FPGAs ACT 3 PCI-Compliant Family • HI m*S M F e a tu re s • Up to 10,000 Gate Array Equivalent Gates. • Highly Predictable, Synthesis-Friendly Architecture Supports High-Level Design Methodologies. . Up to 250 MHz On-Chip Performance.
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20-pin16-bit10kresistorlord8 f01 ad+1mock
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896-Pin
Abstract: smartpower IO290 Axcelerator Family FPGAs
Contextual Info: v2.2 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
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MA 6013
Contextual Info: v2.5 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
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ma 6013 |
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ACTEL CCGA 1152 mechanical
Abstract: AX125 AX2000 CQ208 CQ256 CS180 FG256 PQ208 Trd16 Axcelerator Family FPGAs
Contextual Info: v2.8 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
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actel ccga 1152 mechanicalax125ax2000cq208+6cq256cs180fg256pq208trd16axcelerator family fpgas
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ACTEL CCGA 1152 mechanical
Abstract: lga 4x4 footprint AX125 AX2000 CQ208 CS180 FG256 PQ208 624-Pin tx 434
Contextual Info: v2.7 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
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actel ccga 1152 mechanicallga 4x4 footprintax125ax2000+6cq208cs180fg256pq208624-pintx 434
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GCLR
Abstract: 676P Axcelerator Family FPGAs
Contextual Info: v2.4 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
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AF4 din 74
Abstract: AF2.5 din 74 diode t25 4 g8 Axcelerator Family FPGAs
Contextual Info: v2.5 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
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