A18Q Search Results

CA-180

Abstract: WJ-CA18
Contextual Info: WJ-A18Q/SMA180 10 to 500 MHz TO-8 CASCADABLE AMPLIFIER ♦ AVAILABLE IN SURFACE MOUNT ♦ HIGH REVERSE ISOLATION: 22 dB TYP. ♦ HIGH OUTPUT POWER: +18 dBm (TYP.) Outline Drawings Specifications* Characteristics Frequency (Min.) Small Signal Gain (Min.)

Contextual Info: TMS28F008Axy,TMS28F800Axy 1 048 576 BY 8-BIT/524 288 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SM JS851A-NO VEM BER 1997 - REVISED MARCH 1998 • Organization . . . 1048576 By 8 Bits 524288 By 16 Bits • Array-Blocking Architecture - Two 8K-Byte/4K-Word Parameter Blocks

Contextual Info: HM62W8512B Series 4 M SRAM 512-kword x 8-bit HITACHI ADE-203-904B (Z) Rev. 1.0 Dec. 17, 1998 Description The Hitachi HM62W8512B is a 4-Mbit static RAM organized 512-kword x 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.35 jam Hi-CMOS process

M29F800A3BT12

Abstract: m29f800a3br 29F800A
Contextual Info: Order this document by M29F800A3/D MOTOROLA SEMICONDUCTOR TECHNICAL DATA M29F800A3 M29F800A2 8M CMOS Flash Memory Organization: 524,288 words x 16 bits 1,048,576 words x 8 bits Power Supply Voltage: V q c = 3.3 V ± 0.3 V Access Time: M29F800A3—80 = 80 ns Max

HM628512ALPI-7

Abstract: a12q A17a DP-32 HM628512ALFPI-7 HM628512ALFPI-8 HM628512ALPI-8 HM628512ALTTI-7 Hitachi Scans-001
Contextual Info: HM628512AI Series 524288-word x 8-bit High Speed CMOS Static RAM HITACHI ADE-203-791 Z Preliminary Rev. 0.0 Jun. 20, 1997 D escription T he Hitachi HM 628512A I is a 4-M bit static RAM organized 512-kw ord x 8-bit. It realizes higher density, higher perform ance and low pow er consum ption by em ploying 0 .5 p m H i-C M O S process technology. The

ALY 34

Abstract: 28f800 TMS2800 R-PDSO-G44 Package A10q ALY-34
Contextual Info: TMS28F008Axy,TMS28F800Axy 1 048 576 BY 8-BIT/524 288 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES S M JS 851A - N O VEM BER 1997 - REVISED M ARCH 1998 Organization . . . 1048576 By 8 Bits 524288 By 16 Bits Array-Blocking Architecture - Two 8K-Byte/4K-Word Parameter Blocks

BFJ 64

Contextual Info: 32 0 S 5 - L _ S 5 H- L 7 / 1 5 / 9 8 7 : 5 7 PM P age 1 SHARP LH28F320S5-L/S5H-L LH28F320S5-L/S5H-L 32 M-bit 4 MB x 8/2 MB x 16 Smart 5 Flash Memories (Fast Programming) DESCRIPTION High performance read access time The LH 28F320S 5-L/S5H -L flash m em ories with

29f8008

Abstract: 29F800
Contextual Info: TMS29F800T, TMS29F8O0B 1048576 BY 8-BIT/ 524288 BY 16-BIT FLASH MEMORIES • Single Power Supply Supports 5 V ±10% Read/Write Operation Organization. . . 1048576 By 8 Bits 524288 By 16 Bits Array-Blocking Architecture - One 16K-Byte/One 8K-Word Boot Sector

HM628512BLP-5SL

Abstract: A17a DP-32 HM628512B HM628512BLFP-5 HM628512BLFP-7 HM628512BLP-5 HM628512BLP-7 HM628512BLP-7SL HM628512BLTT7
Contextual Info: HM628512B Series 4 M SRAM 512-kword x 8-bit HITACHI ADE-203-903B (Z) Rev. 1.0 Jan. 13, 1999 Description The Hitachi HM628512B is a 4-Mbit static RAM organized 512-kword x 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.35 (Am Hi-CMOS process technology.

Contextual Info: HM62V8512B Series 4 M SRAM 512-kword x 8-bit HITACHI ADE-203-905 (Z) Preliminary, Rev. 0.0 April 24, 1998 Description The Hitachi HM62V8512B is a 4-Mbit static RAM organized 512-kword x 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.35 (Am Hi-CMOS process technology.

Contextual Info: TMS28F008Axy TMS28F800Axy 8 3 8 8 6 0 8 BOOT-BLOCK FLASH MEMORIES _ * * 1048576 By 8 Bits 524288 By 16 Bits Array-Blocking Architecture - Two 8K-Byte Parameter Blocks - One 96K-Byte Main Block - Seven 128K-Byte Main Blocks - One 16K-Byte Protected Boot Block

a18e

Contextual Info: Preliminary I V t I C MXS3C3S11 3SM-Bit Mask ROM 8/16 Bit Output] FEATURES • Bit organization • Fast access time • Page Size • Current • Supply voltage • Package ORDER INFORMATION 4M x 8 (byte mode 2M x 16 (word mode) Random access: 100ns (max.)

Contextual Info: MX23C8100 MXIC 8M-Bit Mask ROM 8/16 Bit Output FEATURES ORDER INFORMATION Part No. Access Time Package MX23C8100MC-10 100ns 44 pin SOP MX23C8100MC-12 120ns 44 pin SOP MX23C8100MC-15 150ns 44 pin SOP MX23C8100PC-10 100ns 42 pin DIP Standby: 50nA MX23C8100PC-12

Contextual Info: NDCIC MXS3C3S1 □ 3 2 M -B it FEATURES M a s k R O M C B /1 6 B i t O u t p u t ORDER INFORMATION • Bit organization 4M x 8 byte mode) 2M x 16 (word mode) • Fast access time Random access: 100ns (max.) • Current Operating: 60mA Standby: 5|iA • Supply voltage

A17E

Abstract: 56-PIN LH28F320S3H-L LH28F320S3-L
Contextual Info: SHARP LH28F320S3-L/S3H-L LH28F320S3-L/S3H-L 32 M-bit 4 MB x 8/2 MB x 16 Smart 3 Flash Memories (Fast Programming) DESCRIPTION • High performance read access time The LH 28F320S 3-L/S3H -L flash m em ories with Sm art 3 technology are high-density, low-cost,

A17E

Abstract: 56-PIN
Contextual Info: SHARP LH28F320S5-L/S5H-L LH28F320S5-L/S5H-L 32 M-bit 4 MB x 8/2 MB x 16 Smart 5 Flash Memories (Fast Programming) DESCRIPTION • High performance read access time The LH 28F320S 5-L/S5H -L flash m em ories with Sm art 5 technology are high-density, low-cost,

Contextual Info: HM62W8512B Series 4 M SRAM 512-kword x 8-bit HITACHI ADE-203-904 (Z) Preliminary, Rev. 0.0 April 24, 1998 Description The Hitachi HM62W8512B is a 4-Mbit static RAM organized 512-kword x 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.35 (Am Hi-CMOS process

A16Q2

Contextual Info: HM62W8512B Series 4 M SRAM 512-kword x 8-bit HITACHI ADE-203-904B (Z) Rev. 1.0 Dec. 17, 1998 Description The Hitachi HM62W8512B is a 4-Mbit static RAM organized 512-kword x 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.35 ( Am Hi-CMOS process

Contextual Info: TMS28F008Axy,TMS28F800Axy 1 048 576 BY 8-BIT/524 288 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS851A - NOVEMBER 1997 - REVISED MARCH 1998 • Organization . . . 1048576 By 8 Bits 524288 By 16 Bits • Array-Blocking Architecture - Two 8K-Byte/4K-Word Parameter Blocks

29f8008

Abstract: 524288X16
Contextual Info: TMS29F800T, TMS29F800B 1048576 BY 8-BIT/524288 BY 16-BIT FLASH MEMORIES _SMJS8358- MAY 1997 - REVISED OCTOBER 1997 • • • • • • A • • • • Erase Suspend/Resume - Supports Reading Data From, or Programming Data to, a Sector Not Being Erased

AE3G

Abstract: NOR Flash 1996 sector protect
Contextual Info: TMS29LF800T, TMS29LF800B 1048576-BYTE BY 8-BIT/524288-WORD BY 16-BIT 8M-BIT FLASH MEMORIES S M J S 8 2 8 A - S E P T E M B E R 1996 - R E V IS E D MAY 1997 Single Power Supply Supports 2.7-V and 3.6-V Read/Write Operation Erase Suspend/Resume - Supports Reading Data From, or