XRT94L33 Search Results

C4106

Abstract: AD27 I960 XRT94L33 XRT94L33IB
Contextual Info: XRT94L33 333-C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T A T M P P P H A R W A R E M A N U A L CH HA AN NN NE EL LD DS S333///E E333///S ST TS S-111 T TO OS ST TS S-333///S ST TM M-111 M MA AP PP PE ER RS SO ON NE ET TA AT TM

led cross reference

Abstract: XRT94L33 0x0382 0x1151 GR-253-CORE XRT94L33IB 0X176C 0x1738
Contextual Info: XRT94L33 333-C C H A N N E L D S E S T S T O S T S S T M M A P P E R A T M R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S-111 T TO OS ST TS S-333///S ST TM M-111 M MA AP PP PE ER R ––– A AT TM MR RE EG GIIIS ST TE ER RS S March 2007

Contextual Info: DATA SHEET Communications XRT94L33 Features • Provides DS3/ E3 mapping/de-mapping for up to 3 tributaries through SONET STS-1 or SDH AU-3 and/or TUG-3/AU-4 containers • Generates and terminates SONET/SDH section, line and path layers • Integrated SERDES with Clock Recovery Circuit

GR-253-CORE

Abstract: XRT94L33 XRT94L33IB led cross reference 0x0106 0x1950 574 91 256 Sts.1
Contextual Info: XRT94L33 333-C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S-111 T TO OS ST TS S-333///S ST TM M-111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE

XRT94L33IB-F

Abstract: exar XRT94L33IB-L
Contextual Info: PRODUCT CHANGE NOTICE PCN PART NUMBER(S): PCN No.: 08-1211-01 XRT73R12IB-F, XRT75R12IB-F, XRT75R12DIB-F, XRT83L314IB-F, XRT83SL314IB-F, XRT94L31IB-F, XRT94L33IB-F DATE: 12/16/08 PART DESCRIPTION: Please refer to the applicable datasheets at www.exar.com.

telecom bus

Abstract: processor cross reference hdlc sdh 5
Contextual Info: xr PRELIMINARY XRT94L33 APRIL 2002 GENERAL DESCRIPTION The XRT94L33 is a highly integrated SONET/SDH terminator designed for E3/DS3/STS-1 mapping/demapping functions from either the STS-3 or STM-1 data stream. The XRT94L33 interfaces directly to the optical transceiver

AD27

Abstract: I960 XRT94L33 XRT94L33IB TTL RS232 buffer
Contextual Info: xr XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET N0VEMBER 2006 REV.1.2.0. GENERAL DESCRIPTION FEATURES The XRT94L33 is a highly integrated SONET/SDH terminator designed for E3/DS3/STS-1 mapping/de-mapping functions from either the STS-3 or STM-1 data stream. The XRT94L33

0x1758

Abstract: AU-AIS GR-253-CORE XRT94L33 XRT94L33IB ST VIPER application notes 0x11B3 574 91 256
Contextual Info: XRT94L33 333-C C H A N N E L D S E S T S T O S T S S T M M A P P E R S D H R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S-111 T TO OS ST TS S-333///S ST TM M-111 M MA AP PP PE ER R ––– S SD DH HR RE EG GIIIS ST TE ER RS S March 2007

telecom bus

Abstract: processor cross reference
Contextual Info: áç PLIMINARY XRT94L33 APRIL 2002 GENERAL DESCRIPTION The XRT94L33 is a highly integrated SONET/SDH terminator designed for E3/DS3/STS-1 mapping/demapping functions from either the STS-3 or STM-1 data stream. The XRT94L33 interfaces directly to the optical transceiver

75l00d

Contextual Info: áç XRT75L00D E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER NOVEMBER 2003 REV. 1.0.1 • On-chip clock synthesizer provides the appropriate GENERAL DESCRIPTION The XRT75L00D is a single-channel fully integrated Line Interface Unit LIU with Sonet Desynchronizer

chn 834

Abstract: CHN 833 CR69 0X00 GR-253 GR-499-CORE XRT75R12D XRT75R12DIB CHN 703 GR-253 J0 byte length 14
Contextual Info: XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DECEMBER 2006 REV. 1.0.1 GENERAL DESCRIPTION The XRT75R12D is a twelve channel fully integrated Line Interface Unit LIU featuring EXAR’s R3 Technology (Reconfigurable, Relayless Redundancy)

HDB3 CODING DECODING FPGA

Abstract: chn 834 chn 832 R13C7 CHN 833 GR-253 GR-253-CORE GR-499-CORE XRT75R06D FPGA AMI coding decoding
Contextual Info: áç XRT75R06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER DECEMBER 2004 REV. 1.0.0 GENERAL DESCRIPTION The XRT75R06D is a six channel fully integrated Line Interface Unit LIU featuring EXAR’s R3 Technology (Reconfigurable, Relayless, Redundancy) for E3/

JA02

Abstract: ana 608 GR-253 GR-253-CORE GR-499-CORE XRT75L04D XRT75L04DIV chn 347
Contextual Info: áç XRT75L04D FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER NOVEMBER 2003 GENERAL DESCRIPTION The XRT75L04D is a four-channel fully integrated Line Interface Unit LIU with Sonet Desynchronizer for E3/DS3/STS-1 applications. It incorporates four

XR2206 application notes

Abstract: pin diagram of ic xr2206 IC XR2206 XR2206 XR2206 pin details for function generator XR2206 monolithic function generator xr2206 circuit peb1756ae fsk modulation and demodulation using Xr2206 MXP2
Contextual Info: Communications OTN Multi-Service OTN Muxponder/Mapper Ethernet Transport Ethernet over PDH Ethernet over SONET/SDH PDH over SONET/SDH Port Expanders SONET/SDH Multi-Ch/Multi-Rate Framer+Serdes Mappers + Framers Transceivers/CDR PDH E1 LIUs T1/E1/J1 LIUs BITS Solutions

chn 752

Abstract: HDB3 CODING DECODING FPGA chn 501 chn 732
Contextual Info: XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER OCTOBER 2003 REV. 1.0.2 GENERAL DESCRIPTION attenuators can be used for clock smoothing in SONET STS-1 to DS-3 de-mapping. The XRT75L06D is a six channel fully integrated Line

chn 720

Abstract: chn 834 CR170 GR-253 J0 byte length 14
Contextual Info: XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET APRIL 2006 REV. 1.0.1 GENERAL DESCRIPTION The XRT75R12D is a twelve channel fully integrated Line Interface Unit LIU featuring EXAR’s R3 Technology (Reconfigurable, Relayless Redundancy)

Contextual Info: ABOUT EXAR I PRODUCTS I INDEX I SALES INFO I INFORMATION REQUEST I SEARCH I HELP I SONET/SDH Product Tree Click one of the links below to go to that product page SONET/SDH OC-48 Framer XRT95L51 OC-12 POS/ATM Framer XRT95L34 DS3/E3/STS-1 to OC-12 Mapper XRT94L43

GR-253

Abstract: GR-253-CORE GR-499-CORE XRT75L00D XRT75L00DIV XRT75L03 ANSI T1.105.03B 1997 CI 9821 ST CHN 703 chn 347
Contextual Info: XRT75L00D E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER FEBRUARY 2004 REV. 1.0.2 • On-chip clock synthesizer provides the appropriate GENERAL DESCRIPTION The XRT75L00D is a single-channel fully integrated Line Interface Unit LIU with Sonet Desynchronizer

Contextual Info: XRT75R12D PRELIMINARY TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER SEPTEMBER 2003 REV. P1.0.0 GENERAL DESCRIPTION The XRT75R12D is a twelve channel fully integrated Line Interface Unit LIU featuring EXAR’s R3 Technology (Reconfigurable, Relayless Redundancy)

chn 751

Abstract: GR-253 GR-253-CORE GR-499-CORE XRT75R06D XRT75R06DIB chn 622 st WG 253 chn 834 HDB3 CODING DECODING FPGA
Contextual Info: xr XRT75R06D PRELIMINARY SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER JULY 2004 REV. 1.0.0 GENERAL DESCRIPTION The XRT75R06D is a six channel fully integrated Line Interface Unit LIU featuring EXAR’s R3 Technology (Reconfigurable, Relayless, Redundancy) for E3/

GR-253

Abstract: GR-253-CORE GR-499-CORE XRT75L02D XRT75L03 D6/chn 609
Contextual Info: áç XRT75L02D TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER NOVEMBER 2003 GENERAL DESCRIPTION REV. 1.0.1 • Provides low jitter clock outputs for either DS3,E3 or STS-1 rates. The XRT75L02D is a two-channel fully integrated Line Interface Unit LIU with Sonet Desynchronizer

Contextual Info: Hardware Manual, P1.0.1, October 2005 INTEGRATED 28-CHANNEL T1/E1 LIU/FRAMER, VT/TU MAPPER AND M13 MULTIPLEXER XRT86SH328 Network & Transmission Products XRT86SH328 Hardware Manual GENERAL DESCRIPTION 1 GENERAL DESCRIPTION • Supports 21 E1 mapped as Asynchronous VT2 into an

N30 transformer core

Abstract: transformer e19 GR-253-CORE XRT86SH328 XRT86SH328IB
Contextual Info: Datasheet, P1.0.1, September 2005 INTEGRATED 28-CHANNEL T1/E1 LIU/FRAMER, VT/TU MAPPER AND M13 MULTIPLEXER XRT86SH328 Network & Transmission Products XRT86SH328 Datasheet GENERAL DESCRIPTION 1 GENERAL DESCRIPTION • Supports 21 E1 mapped as Asynchronous VT2 into an

MCP860

Contextual Info: Hardware Manual, P1.0.4, March 2006 INTEGRATED 28-CHANNEL T1/E1 LIU/FRAMER, VT/TU MAPPER AND M13 MULTIPLEXER XRT86SH328 Network & Transmission Products XRT86SH328 Hardware Manual GENERAL DESCRIPTION 1 GENERAL DESCRIPTION • Supports 21 E1 mapped as Asynchronous VT2 into an