SN74LVC821 Search Results

Contextual Info: SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS304J – MARCH 1993 – REVISED FEBRUARY 2005 FEATURES • • • • • • • • • DB, DGV, DW, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

SN74LVC821A

Contextual Info: SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS304F – MARCH 1993 – REVISED JUNE 1998 D D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS304J – MARCH 1993 – REVISED FEBRUARY 2005 FEATURES • • • • • • • • • DB, DGV, DW, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

Contextual Info: SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS304J – MARCH 1993 – REVISED FEBRUARY 2005 FEATURES • • • • • • • • • DB, DGV, DW, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

Contextual Info: SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS304F – MARCH 1993 – REVISED JUNE 1998 D EPIC Enhanced-Performance Implanted D D D D D D D DB, DW, OR PW PACKAGE (TOP VIEW CMOS) Submicron Process Typical VOLP (Output Ground Bounce)

SN74LVC821A

Abstract: SN74LVC821ADBR SN74LVC821ADW SN74LVC821ADWR SN74LVC821ANSR
Contextual Info: SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS304I – MARCH 1993 – REVISED AUGUST 2002 D D D D D D D D D DB, DGV, DW, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 7.3 ns at 3.3 V

SN74LVC821A

Abstract: SN74LVC821ADBR SN74LVC821ADW SN74LVC821ADWR SN74LVC821ANSR SN74LVC821APW LVC821
Contextual Info: SN74LVC821A 10ĆBIT BUSĆINTERFACE FLIPĆFLOP WITH 3ĆSTATE OUTPUTS SCAS304J − MARCH 1993 − REVISED AUGUST 2003 D D D D D D D D D DB, DGV, DW, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 7.3 ns at 3.3 V

Contextual Info: SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS304J – MARCH 1993 – REVISED FEBRUARY 2005 FEATURES • • • • • • • • • DB, DGV, DW, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

Contextual Info: SN74LVC821 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS _ SCAS304A - MARCH 1993 - REVISED JULY 1995 • EPIC Enhanced-Performance Implanted CMOS Submicron Process d b , dw , o r pw pa c ka g e VIEW> • Typical V q l p (Output Ground Bounce)

Contextual Info: SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS304E - MARCH 1993 - REVISED JANUARY 1998 • Typical V q l p Output Ground Bounce < 0.8 V at Vc c = 3.3 V, TA = 25°C • Typical V q h v (Output Vqh Undershoot) > 2 V at VCc = 3-3 V, TA = 25°C

SN74LVC821

Contextual Info: SN74LVC821 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS304A – MARCH 1993 – REVISED JULY 1995 D D D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN74LVC821 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS MARCH 1993 • • Space-Saving Package Option: Shrink Small-Outline Package DB Features EIAJ 0.65-mm Lead Pitch EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Designed to Facilitate Incident Wave

Contextual Info: SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS304F – MARCH 1993 – REVISED JUNE 1998 D D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C

SN74LVC821

Contextual Info: SN74LVC821 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS304A – MARCH 1993 – REVISED JULY 1995 D D D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS304J – MARCH 1993 – REVISED AUGUST 2003 D D D D D D D D D DB, DGV, DW, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 7.3 ns at 3.3 V

LC821A

Contextual Info: SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS304I – MARCH 1993 – REVISED AUGUST 2002 D D D D D D D D D DB, DGV, DW, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 7.3 ns at 3.3 V

Contextual Info: SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS304J – MARCH 1993 – REVISED FEBRUARY 2005 FEATURES • • • • • • • • • DB, DGV, DW, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

10D-11

Abstract: SN74LVC821A
Contextual Info: SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SC AS304E - M ARCH 1993 - R EVISED JA N U A R Y 1998 D D D D D D EPIC Enhanced-Performance Implanted CMOS Submicron Process db, dw , o r pw package (t o p Typical V q l p (Output Ground Bounce)

10D-11

Abstract: SN74LVC821A
Contextual Info: SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS S C A S304D - M ARCH 1 993 - R EVISED JU N E 1997 • EPIC Enhanced-Performance Implanted CMOS Submicron Process db, dw , o r pw package (t o p • Typical V q lp (Output Ground Bounce) < 0.8 V at VCc = 3.3 V, TA = 25°C

SN74LVC821A

Abstract: SN74LVC821ADBR SN74LVC821ADW SN74LVC821ADWR SN74LVC821ANSR LC821A
Contextual Info: SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS304J – MARCH 1993 – REVISED FEBRUARY 2005 FEATURES • • • • • • • • • DB, DGV, DW, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

SN74LVC821A

Abstract: SN74LVC821ADBR SN74LVC821ADW SN74LVC821ADWR SN74LVC821ANSR LC821A
Contextual Info: SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS304J – MARCH 1993 – REVISED FEBRUARY 2005 FEATURES • • • • • • • • • DB, DGV, DW, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

LC821A

Contextual Info: SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS304J – MARCH 1993 – REVISED FEBRUARY 2005 FEATURES • • • • • • • • • DB, DGV, DW, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

Contextual Info: SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS304J – MARCH 1993 – REVISED FEBRUARY 2005 FEATURES • • • • • • • • • DB, DGV, DW, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

SN74LVC821A

Contextual Info: SN74LVC821A 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS304D – MARCH 1993 – REVISED JUNE 1997 D D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C