JESD17 Search Results

Contextual Info: SN54AHC126, SN74AHC126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SC LS257E-D EC EM BER 1995-R E V IS E D FEBRUARY 1998 Operating Range 2-V to 5.5-V Vqq EP/C Enhanced-Performance Implanted CMOS Process High Latch-Up Immunity Exceeds 250 mA Per JESD17

Contextual Info: SN74AHCT1G08 SINGLE 2-INPUT POSITIVE-AND GATE S C LS 315E -M AR C H 1996-R E V IS E D FEBRUARY 1998 • Inputs Are TTL-Voltage Compatible • EP/C Enhanced-Performance Implanted CMOS Process • Latch-Up Performance Exceeds 250 mA Per JESD17 • Package Options Include Plastic

Contextual Info: SN54AHCT126, SN74AHCT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS265I-DECEMBER 1995-REVISED FEBRUARY 1998 * • Inputs AreTTL-VoltageCompatible EP/C Enhanced-Performance Implanted CMOS Process High Latch-Up Immunity Exceeds 250 mA Per JESD17

Contextual Info: SN74AHC1G14 SINGLE SCHMITT-TRIGGER INVERTER GATE SCLS321E - MARCH 1996 - REVISED JANUARY 1998 • Operating Range 2-V to 5.5-V V qq • EP/C Enhanced-Performance Implanted CMOS Process • High Latch-Up Immunity Exceeds 250 mA Per JESD17 • ESD Protection Exceeds 2000 V Per

Contextual Info: SN74AHC1G32 SINGLE 2-INPUT POSITIVE-OR GATE SCLS317E - MARCH 1996 - REVISED JANUARY 1998 • Operating Range 2-V to 5.5-V V qq • EP/C Enhanced-Performance Implanted CMOS Process • High Latch-Up Immunity Exceeds 250 mA Per JESD17 • Package Options Include Plastic

322F-M

Contextual Info: SN74AHCT1G14 SINGLE SCHMITT-TRIGGER INVERTER GATE S C LS 322F-M A R C H 1996-R E V IS ED FEBRUARY 1998 DBV PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EP/C (Enhanced-Performance Implanted CMOS) Process High Latch-Up Immunity Exceeds 250 mA Per JESD17

Contextual Info: SN74AHC1G04 SINGLE INVERTER GATE SCLS318E - MARCH 1996 - REVISED JANUARY 1998 • • • • • Operating Range 2-V to 5.5-V Vqq EP/C Enhanced-Performance Implanted CMOS Process High Latch-Up Immunity Exceeds 250 mA Per JESD17 DBV OR DCK PACKAGES (TOP VIEW)

1996-R

Abstract: sn74ahc1g08
Contextual Info: SN74AHC1G08 SINGLE 2-INPUT POSITIVE-AND GATE SC LS 314D -M A R C H 1996-R E V IS E D FEBRUARY 1998 * Operating Range 2-V to 5.5-V V qq * EP/C Enhanced-Performance Implanted CMOS Process * Latch-Up Performance Exceeds 250 mA Per JESD17 * Package Options Include Plastic

Contextual Info: SN74AHC1G00 SINGLE 2-INPUT POSITIVE-NAND GATE SCLS313D-MARCH 1996-REVISED FEBRUARY 1998 Operating Range 2-V to 5.5-V V qq DBV OR DCK PACKAGE TOP VIEW EP/C (Enhanced-Performance Implanted CMOS) Process Latch-Up Performance Exceeds 250 mA Per JESD17 Package Options Include Plastic

Contextual Info: SN74AHCT1G32 SINGLE 2-INPUT POSITIVE-OR GATE S C LS 320E -M AR C H 1996-R E V IS E D FEBRUARY 1998 • Inputs Are TTL-Voltage Compatible • EP/C Enhanced-Performance Implanted CMOS Process • Latch-Up Performance Exceeds 250 mA Per JESD17 • Package Options Include Plastic

A1619A

Abstract: b1241
Contextual Info: SN54ABT32318, SN74ABT32318 18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS SCBS180A-JUNE 1 9 9 2 - REVISED JULY 1994 Members of the Texas Instruments Wldebus+ Family State-of-the-Art EPIC-IlB™ BICMOS Design Significantly Reduces Power Dissipation Typical V q l p Output Ground Bounce

1d4 cb

Contextual Info: SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS S CB S160 - DE CE M B E R 1992 Members of the Texas Instruments Widebus Family SN54ABT16373A . . . WD PACKAGE SN74ABT16373A . . . DGG OR DL PACKAGE TOP VIEW State-of-the-Art EPIC-llB™ BiCMOS Design

Contextual Info: SN74LVC540 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS JA N U A R Y 1993 • Space-Saving Package Option: Shrink Small-Outline Package DB Features EIAJ 0.65-mm Lead Pitch DB, DW, OR PW PACKAGE (TOP VIEW) • EPIC (Enhanced-Performance implanted CMOS) Submicron Process

CO2V

Contextual Info: SN74ALVC16600 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS JA N U A R Y 1993 Member of the Texas Instruments Widebus Family DGG OR DL PACKAGE TOP VIEW ÖEÄE [ LEAB [ A1 [ GND [ A2 [ A3 [ EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process

51A-2

Contextual Info: SN54ABT16470, SN74ABT16470 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS S CBS085B - D3794, FEBR UARY 1991 - R EVISED JULY 1993 SN54ABT16470. . WD P ACKAG E SN74ABT16470. . DL P ACKAG E TOP VIEW Members of the Texas Instruments Widebus Family State-of-the-Art EPIC-UB ™ BiCMOS Design

ABT16374A

Contextual Info: SN54ABT16374A, SN74ABT16374A 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS MARCH 1993-R EV IS ED JULY 1993 Members of the Texas Instruments Widebus Family State-of-the-Art EPIC-HB" BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per

Contextual Info: SN74LVC841 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS M ARCH 1993 OB, DW, OR PW PACKAGE TOP VIEW • Space-Saving Package Option: Shrink Small-Outline Package (DB) Features EIAJ 0.65-mm Lead Pitch • EPIC (Enhanced-Performance Implanted

SN54LV14

Abstract: 2020CN
Contextual Info: SN54LV14, SN74LV14 HEX SCHMITT-TRIGGER INVERTERS _ S C L S 1 8 7 B - FEBRUARY 1 9 9 3 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-|i Process SN54LV14 . . . J OR W PACKAGE SN74LV14. . . D, DB, OR PW PACKAGE (TOP VIEW) TVplcal V q l p (Output Ground Bounce)

Contextual Info: SN74LVC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET JANUARY 1993 D, DB, OR PW PACKAGE TOP VIEW • EPIC (Enhanced-Performance Implanted 1CCR [ 1 1D [ 2 CMOS) Submicron Process • 1CLK [ 3 Designed to Facilitate Incident Wave

Contextual Info: SN54LVU04, SN74LVU04 HEX INVERTERS S C L S 1 B 5 B - FEBRUARY 1993 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-n Process Typical V q l p (Output Ground Bounce) < 0.8 V at V c c . Ta = 25°C Typical V q h v (Output V q h Undershoot)

Contextual Info: SN54ABT16501, SN74ABT16501 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS _ SCBS086C - FEBRUARY 1991 - REVISED JANUARY 1997 Members of the Texas Instruments Widebus Family SN54ABT16501 . . . W D PACKAGE SN74ABT16501 . . . DGG OR DL PACKAGE

Contextual Info: SN74ALVC16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS JANUARY 1993 DGG OR DL PACKAGE TOP VIEW UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode

Contextual Info: SN74LVC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCAS279B-JANUARY 1993 - REVISED JULY 1995 I • EP/C Enhanced-Performance Implanted CMOS Submicron Process • ESD Protection Exceeds 2000 V Per MII-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

d3798

Abstract: ABT16543
Contextual Info: SN54ABT16543, SN74ABT16543 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS087A - D379B, FEBRUARY 1991 - R EVISED O CTO BER 1992 Members of the Texas Instruments Widebus Family State-of-the-Art EPIC-llB™ BiCMOS Design Significantly Reduces Power Dissipation