SN74AC Search Results

CT 2048

Abstract: D8228
Contextual Info: SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L 2048 x 9,4096 x 9,8192 x 9,16384 x9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS226A - FEBRUARY 1993 - REVISED SEPTEMBER 1995 Reads and Writes Can Be Asynchronous or Coincident Organization: - SN74ACT7203L - 2048 x 9

Contextual Info: SN74ACT7881 1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227C - FEBRUARY 1993 - REVISED FEBRUARY 1996 • Member of the Texas Instruments Wldebus Family • Independent Asynchronous Inputs and Outputs • Input-Ready, Output-Ready, and Half-Full Flags

Contextual Info: SN74ACT2235 1024x9x2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS148E - DECEMBER 1990 - REVISED APRIL 1998 • Independent Asynchronous Inputs and Outputs • Access Times of 25 ns With a 50-pF Load • Data Rates up to 50 MHz • Low-Power Advanced CMOS Technology

Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET _SCASS21C- AUGUST 199S - REVISED SEPTEMBER 1996 EPIC Enhanced-Performance Implanted CMOS 1-|im Process SN54AC74 . . . J OR W PACKAGE SN74AC74 . . . D, DB, N, OR PW PACKAGE

SN74ACTOO

Contextual Info: SN54ACT00, SN74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES S C A S 5 2 3 A -AU G U S T 199S - R E V IS E D MAY 1996 Inputs Are TTL-Voltage Compatible EPIC Enhanced-Performance Implanted CMOS 1-ixm Process Package Options Include Plastic Small-Outllne (D), Shrink Small-Outllne

Contextual Info: SN74ACT7201A-25, SN74ACT7201A-35, SN74ACT7201A-50 512 x 9 ASYNCHRONOUS FIRST-IN FIRST-OUT MEMORY D3101. MARCH 1988 • Asynchronous Operation S N 74A C T72 01A . . . N PACKAGE TOP VIEW • Lower Power Consumption Active . . . 400 mW Power Down . . . 3 mW

Contextual Info: SN54AC534, SN74AC534 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS554A – NOVEMBER 1995 – REVISED MAY 1996 D D D SN54AC534 . . . J OR W PACKAGE SN74AC534 . . . DB, DW, N, OR PW PACKAGE TOP VIEW 3-State Inverting Outputs Drive Bus Lines

SN54AC04

Contextual Info: SN54AC04, SN74AC04 HEX INVERTERS SCAS519C – JULY 1995 – REVISED SEPTEMBER 1996 D D EPIC  Enhanced-Performance Implanted CMOS 1-µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW)

Contextual Info: SN54AC240, SN74AC240 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS512C – JUNE 1995 – REVISED SEPTEMBER 1996 D EPIC  Enhanced-Performance Implanted CMOS 1-µm Process Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and

Contextual Info: SN54AC08, SN74AC08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCAS536B – SEPTEMBER 1995 – REVISED SEPTEMBER 1996 D EPIC  Enhanced-Performance Implanted CMOS 1-µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW)

Contextual Info: SN54AC32, SN74AC32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCAS528B – AUGUST 1995 – REVISED SEPTEMBER 1996 D EPIC  Enhanced-Performance Implanted CMOS 1-µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW)

Contextual Info: SN54ACT563, SN74ACT563 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS550A – NOVEMBER 1995 – REVISED 1996 D D D SN54ACT563 . . . J OR W PACKAGE SN74ACT563 . . . DB, DW, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible 3-State Inverted Outputs Drive Bus Lines

Contextual Info: SN54AC240, SN74AC240 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS512C – JUNE 1995 – REVISED SEPTEMBER 1996 D EPIC  Enhanced-Performance Implanted CMOS 1-µm Process Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and

Contextual Info: SN54ACT00, SN74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCAS523B – AUGUST 1995 – REVISED AUGUST 1999 D D D SN54ACT00 . . . J OR W PACKAGE SN74ACT00 . . . D, DB, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EPIC  (Enhanced-Performance Implanted

Contextual Info: SN54ACT14, SN74ACT14 HEX SCHMITT-TRIGGER INVERTER SCAS557D – DECEMBER 1995 – REVISED MARCH 1998 D D D Inputs Are TTL-Voltage Compatible EPIC  Enhanced-Performance Implanted CMOS 1-µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline

Contextual Info: SN54ACT241, SN74ACT241 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS516B – JUNE 1995 – REVISED MAY 1996 D SN54ACT241 . . . J OR W PACKAGE SN74ACT241 . . . DB, DW, N, OR PW PACKAGE TOP VIEW Inputs Are TTL Compatible EPIC  (Enhanced-Performance Implanted

Contextual Info: SN54AC240, SN74AC240 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS512C – JUNE 1995 – REVISED SEPTEMBER 1996 D EPIC  Enhanced-Performance Implanted CMOS 1-µm Process Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and

Contextual Info: SN54ACT00, SN74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCAS523B – AUGUST 1995 – REVISED AUGUST 1999 D D D SN54ACT00 . . . J OR W PACKAGE SN74ACT00 . . . D, DB, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EPIC  (Enhanced-Performance Implanted

Contextual Info: SN54AC11, SN74AC11 TRIPLE 3ĆINPUT POSITIVEĆAND GATES SCAS532D − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 7.5 ns at 5 V 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3A 3B 3C 3Y 2A NC 2B NC

Contextual Info: SN54AC11, SN74AC11 TRIPLE 3ĆINPUT POSITIVEĆAND GATES SCAS532D − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 7.5 ns at 5 V 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3A 3B 3C 3Y 2A NC 2B NC

Contextual Info: SN74AC32ĆEP QUADRUPLE 2ĆINPUT POSITIVEĆOR GATE SCAS720 − OCTOBER 2003 D Controlled Baseline D D D D D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 7.5 ns at 5 V − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of

Contextual Info: SN74ACT16374Q-EP 16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS SCAS679B – MAY 2002 – REVISED JULY 2002 D D D D D D D D D D DL PACKAGE TOP VIEW Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of

Contextual Info: SN74ACT08ĆEP QUADRUPLE 2ĆINPUT POSITIVEĆAND GATE SCAS779 − SEPTEMBER 2004 D Controlled Baseline D D D D D Inputs Accept Voltages to 5.5 V D Max tpd of 10 ns at 5 V D Inputs Are TTL-Voltage Compatible − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing

Contextual Info: SN74AC08ĆEP QUADRUPLE 2ĆINPUT POSITIVEĆAND GATE SCAS718 − OCTOBER 2003 D Controlled Baseline D D D D D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 7.5 ns at 5 V − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of