NX64KBPS Search Results

MT9075

Abstract: E1 to ethernet converter circuit "network interface cards"
Contextual Info: MT90210 Multi-Channel Parallel Access Circuit Features & Benefits Guide September 14, 1998 Revision 1.0 MT90210 Features & Benefits Guide Product Summary The MT90210 is a Multi-rate Parallel Access Circuit, that allows streaming of DS0 and Nx64Kbps streams between an isochronous serial TDM bus and a

ATM circuit diagram

Abstract: MT90220 MT9045 MT90503 MT90528 MT9072 MT9076 VTOA-0078
Contextual Info: AAL1 SAR MT90503 Network Connectivity The MT90503 is a multi-channel ATM Adaptation Layer 1 AAL1 segmentation and reassembly (SAR) device that interfaces serial stream voice and data traffic from the TDM bus to the ATM network. The device provides the industry’s

Contextual Info: Rev: 032609 DS34S101, DS34S102, DS34S104, DS34S108 Single/Dual/Quad/Octal TDM-over-Packet Chip General Description These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC compliant devices allow up to eight E1, T1 or serial streams or one high-speed E3, T3, STS-1 or serial

ATM circuit diagram

Abstract: MT9072 MT9076 MT90220 MT9045 MT90503 MT90528
Contextual Info: AAL1 SAR Network Connectivity MT90503 Highest Integration The MT90503 is a multi-channel ATM Adaptation Layer 1 AAL1 segmentation and reassembly (SAR) device that interfaces serial stream voice and data traffic from the TDM bus to the ATM network. The device provides the industry’s highest integration—

RESREF

Abstract: DS34T108 MDIO MDC
Contextual Info: ABRIDGED DATA SHEET Rev: 121407 DS34T101/DS34T102/DS34T104/DS34T108 Single/Dual/Quad/Octal TDM-Over-Packet Chip General Description The IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC draft-compliant DS34T108 allows up to eight T1/E1 links or frame-based serial HDLC links to be

Contextual Info: Rev: 032609 DS34S101, DS34S102, DS34S104, DS34S108 Single/Dual/Quad/Octal TDM-over-Packet Chip General Description These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC compliant devices allow up to eight E1, T1 or serial streams or one high-speed E3, T3, STS-1 or serial

RJ48X

Abstract: USOC RJ48C TR54016 rate-based ABR modem rate-based traffic control IA-64
Contextual Info: D E V E L O P E R ’ S I N T E R F A C E G U I D E F O R I A - 6 4 S E R V E R S DIG64 Technical Whitepaper: IA-64 Server Network Communications Solutions Intel Corporation January 2000 THIS DOCUMENT IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER,

RLOF 100

Abstract: DS34t108 TDM8
Contextual Info: ABRIDGED DATA SHEET Rev: 072707 DS34T101/DS34T102/DS34T104/DS34T108 Single/Dual/Quad/Octal TDM-Over-Packet Chip General Description 3 The IETF PWE SAToP/CESoPSN/TDMoIP/HDLC draft-compliant DS34T108 allows up to eight T1/E1 links or frame-based serial HDLC links to be

BFAP20

Abstract: samsung ltcc G.SHDSL Industry Single-Chip VTSA7 447h LQ13 tag 9018 LM 205h 276 741h EoPDH
Contextual Info: Rev: 063008 DS33X162/DS33X161/DS33X82/DS33X81/ DS33X42/DS33X41/DS33X11/DS33W41/DS33W11 Ethernet Over PDH Mapping Devices General Description The DS33X162 family of semiconductor devices extend 10/100/1000Mbps Ethernet LAN segments by encapsulating MAC frames in GFP-F, HDLC, cHDLC,

DS34T104GN

Abstract: 3216 footprint IPC TDM8 DS34T101GN DS34T102GN DS34T104 DS34T108GN 7U22 DS34T10x
Contextual Info: Rev: 072707 DS34T101/DS34T102/DS34T104/DS34T108 Single/Dual/Quad/Octal TDM-Over-Packet Chip General Description 3 The IETF PWE SAToP/CESoPSN/TDMoIP/HDLC draft-compliant DS34T108 allows up to eight T1/E1 links or frame-based serial HDLC links to be transported transparently through a switched IP or

diode CH9d

Abstract: CH7C diode CH8C diode diode ch6b rg703 Diode TS21C diode code eb13 RFC-5087 10407C 2125S
Contextual Info: 19-4835; 8/09 DS34T101, DS34T102, DS34T104, DS34T108 Single/Dual/Quad/Octal TDM-over-Packet Chip General Description These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC compliant devices allow up to eight E1, T1 or serial streams or one high-speed E3, T3, STS-1 or serial

Contextual Info: ABRIDGED DATA SHEET Rev: 072707 DS34T101/DS34T102/DS34T104/DS34T108 Single/Dual/Quad/Octal TDM-Over-Packet Chip General Description The IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC draft-compliant DS34T108 allows up to eight T1/E1 links or frame-based serial HDLC links to be

MT90520

Abstract: MT90528 ATM circuit diagram
Contextual Info: SEGMENTATION & REASSEMBLY SAR PRODUCT OVERVIEW The MT90520 and MT90528 are AAL1 (ATM Adaptation Layer 1) segmentation and reassembly (SAR) devices designed to optimize performance and cost efficiency of TDM-to-ATM conversion applications. The devices are the first AAL1 SARs with on-chip per-port PLLs that provide a total

Contextual Info: Rev: 012108 DS33X162/DS33X161/DS33X82/DS33X81/ DS33X42/DS33X41/DS33X11/DS33W41/DS33W11 Ethernet Over PDH Mapping Devices General Description The DS33X162 family of semiconductor devices extend 10/100/1000Mbps Ethernet LAN segments by encapsulating MAC frames in GFP-F, HDLC, cHDLC,

Contextual Info: Rev: 063008 DS3 3 X 1 6 2 /DS3 3 X 1 6 1 /DS3 3 X 8 2 /DS3 3 X 8 1 / DS3 3 X 4 2 /DS3 3 X 4 1 /DS3 3 X 1 1 /DS3 3 W4 1 /DS3 3 W1 1 Et he r ne t Ove r PDH M a pping Devic e s Ge ne ra l De sc ript ion The DS33X162 family of semiconductor devices extend 10/100/1000Mbps Ethernet LAN segments by

CRC-10

Abstract: MXT3010 MXT3020-C MXT3020-C33 MXT3020-C40 MXT3020-C60 multiplexing e1 frame to e3 frame
Contextual Info: M X T 3 0 2 0 Circuit Coprocessor for ATM Typical Applications WAN access “common card” services • AAL1-SDT, AAL1-UDT, AAL2, AAL5 • Inverse Multiplexing for ATM IMA • Cell Relay (T1/E1 UNI) • Frame Relay with external hardware • Circuit Emulation

e1 E2 e3 liu transceiver

Contextual Info: PRELIMINARY-SUBJECT TO CHANGE ABRIDGED DATA SHEET Rev: 091407 DS34S101//DS34S102/DS34S104/DS34S108 Single/Dual/Quad/Octal TDM-Over-Packet Transport Devices General Description The IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC draft-compliant DS34S108 allows up to eight T1/E1

samsung ltcc

Contextual Info: PRELIMINARY Rev: 060607 DS33X162/DS33X161/DS33X82/DS33X81/ DS33X42/DS33X41/DS33X11/DS33W41/DS33W11 Ethernet Over PDH Mapping Devices General Description The DS33X162 family of semiconductor devices extend 10/100/1000Mbps Ethernet LAN segments by encapsulating MAC frames in GFP-F, HDLC, cHDLC,

Contextual Info: Rev: 060607 DS33X162/DS33X161/DS33X82/DS33X81/ DS33X42/DS33X41/DS33X11/DS33W41/DS33W11 Ethernet Over PDH Mapping Devices General Description ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Y ♦ ♦ 10/100/1000 IEEE 802.3 MAC MII/RMII/GMII with Autonegotiation and Flow Control

Contextual Info: ABRIDGED DATA SHEET Rev: 040108 DS34S101//DS34S102/DS34S104/DS34S108 Single/Dual/Quad/Octal TDM-Over-Packet Transport Devices General Description The IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC RFC-compliant DS34S108 allows up to eight T1/E1 links or frame-based serial HDLC links to be

Ee 19c transformer

Abstract: PCF7 sace e3 sace e2 i386ex rj48 to db9 VG96 386EX 1N4148 and/pcf7 FALC54
Contextual Info: ICs for Communications Evaluation System for Interworking Element IWE8 EASY4220 Version 1.1 with PXB 4220 IWE8 Version 1.1 PEB 2254 FALC54 Version 1.3 Tool Description 06.97 DS 1 EASY4220 Revision History: Current Version: 06.97 Previous Version: None Page

MT9045

Abstract: MT90520 MT90528 MT9072 MT9076
Contextual Info: AAL1 SAR Network Connectivity MT90520/28 Complimentary Products SARs, IMAs, Framers, Digital PLLs, TDM to IP processors Reduced Board Space & System Cost On-chip per-port PLLs synchronize inputs to different network clocks, eliminating up to four external framers,

DS34T101

Abstract: D2048 DS34S101 DS34S102 DS34T104 DS34T101GN DS34T102GN DS34T104GN DS34T108GN RFC4553
Contextual Info: ABRIDGED DATA SHEET Rev: 042608 DS34T101/DS34T102/DS34T104/DS34T108 Single/Dual/Quad/Octal TDM-Over-Packet Chip General Description The IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC draft-compliant DS34T108 allows up to eight T1/E1 links or frame-based serial HDLC links to be