LH521028 Search Results

Contextual Info: LH521028 FEATURES • Fast Access Times: 17/20/25/35 ns • Wide Word 18-Bits for: - Improved Performance - Reduced Component Count - Nine-bit Byte for Parity • Transparent Address Latch • Reduced Loading on Address Bus • Low-Power Stand-by Mode when

LH521028

Abstract: LH521028A 521028-1D
Contextual Info: LH521028A A14 A13 G A15 VSS ALE VCC VSS 9 W DQ10 4 3 2 1 52 51 50 49 48 47 46 DQ8 45 DQ7 10 44 DQ6 11 43 VCC DQ11 12 42 VSS DQ12 13 41 DQ5 DQ13 14 40 DQ4 DQ14 15 39 DQ3 DQ2 VSS 16 38 VCC 17 37 VSS DQ15 18 36 VCC DQ0 A11 DQ1 34 A12 35 20 21 22 23 24 25 26 27 28 29 30 31 32 33

Contextual Info: LH521028 FEATURES • Fast Access Times: 17/20/25/35 ns • Wide Word 18-Bits for: - Improved Performance - Reduced Component Count - Nine-bit Byte for Parity • Transparent Address Latch • Reduced Loading on Address Bus • Low-Power Stand-by Mode when

LH521028

Abstract: xmxxx
Contextual Info: LH521028 CMOS 64K x 18 Static RAM operations on the high and the low bytes. The Address Latches are transparent when ALE is HIGH for applica­ tions not requiring a latch , and are latched when ALE is LOW. The Address Latches and the wide word help to eliminate the need for external Addressbusbuffers and/or

Contextual Info: LH521028 CMOS 64K x 18 Static RAM FEATURES • Fast Access Times: 17/20/25/35 ns • Wide Word 18-Bits for: - Improved Performance - Reduced Component Count - Nine-bit Byte for Parity • Transparent Address Latch • Reduced Loading on Address Bus • Low-Power Stand-by Mode when

LH521028U-25

Abstract: LH521028
Contextual Info: LH521028 FEATURES • Fast Access Times: 17/20/25/35 ns • Wide Word 18-Bits for: – Improved Performance – Reduced Component Count – Nine-bit Byte for Parity • Transparent Address Latch • Reduced Loading on Address Bus • Low-Power Stand-by Mode when

Contextual Info: LH521028 FEATURES • Fast Access Times: 20/25/35 ns • Wide Word 18-Bits for: - Improved Performance - Reduced Component Count - Nine-bit Byte for Parity Transparent Address Latch • Reduced Loading on Address Bus • Low Power Stand-by Mode when Deselected

LH521028

Abstract: LH521028A
Contextual Info: LH521028A ALE 1 52 51 50 49 48 47 46 A14 2 A13 3 G 4 A15 VSS 5 W 6 DQ8 45 DQ7 10 44 DQ6 11 43 VCC DQ11 12 42 VSS DQ12 13 41 DQ5 DQ13 14 40 DQ4 DQ14 15 39 DQ3 DQ2 DQ10 9 VCC VSS 18 36 VCC DQ16 19 35 DQ1 DQ17 34 20 21 22 23 24 25 26 27 28 29 30 31 32 33 DQ0

Contextual Info: PRELIMINARY INFORMATION CMOS 64K x 18 Static RAM FEATURES • Fast Access Times: 20/25/30/35 ns • Space Saving 52-Pin PLCC • JEDEC Standard Pinout • Wide Word 18-Bits for: - Improved Performance - Reduced Component Count - Nine-bit Byte for Parity

lh57257

Abstract: IR2E31 IR2E01 IR2C07 IR2E27 IR2E24 IR2E19 IR2E31A IR3n06 IR2E02
Contextual Info: Index Model No. ARM7D CPU Core Bi-CMOS 1 27 40,42 _ _ CMOS CMOS CMOS CMOS CMOS 4A 5A 8 A AH D ID1 Series ID2 Series 40,42 40.42 40,42 40,42 40 B ü.’1*"! 14,15 14 m IR2339 IR2403 IR2406 IR2406G IR2410 IR2411 IR2415 IR2419 IR2420 IR2422 IR2425 IR2429

Contextual Info: MEMORIES * S tic RAMs Process C apacity Configuration Model No. A ccess tim e ns 70 80 90 100 120 LH5116 16k Full CMOS 64k 2k X 8 8k X 8 LH5116H f- Supply voltage : 5 V * 10% QpewBng tew ^raw » : ~ 40to85'C LH5116S j- Supply voltage : 3 V ± 10% LH5164A

BNK-17

Contextual Info: MEMORIES ★Under development • S ta tic RA M s Process Capacity Configuration words X bits Modal No. 2k X 8 Full CMOS 64k 8k X 8 256k 32k X 8 64k 8k X 8 64k X 4 256k 32k X 8 64k X 8 CMOS periphery 100 40/0.001 5 ± 10% O to 70 100 40/0.001 5 ± 10% - 4 0 to 85

LH5160N

Abstract: LH5115 LH5118D LH5160 LH5160D LH521000 LH5167 LH52252A LH5114H LH5911-55
Contextual Info: NOV 0 5 1990 L H 5 9 1 1 /L H 5 9 1 2 /L H 5 9 1 4 2K x 8 CMOS Dual Port RAM Preliminary Data Sheet Features Functional Description The IH 5911, LH5912 and LH5914are dual port static RAMs that use true dual port memory cells to allow each port to independently access any location in memory.

Contextual Info: CMOS 64K x 18 Static RAM FEATURES • Fast Access Times: 15/17/20/25/35 ns • Wide Word 18-Bits for. - Improved Performance - Reduced Component Count - Nine-bit Byte for Parity • Transparent Address Latch • Reduced Loading on Address Bus • Low-Power Stand-by Mode when

organizational structure samsung

Abstract: NMS256X8 MICRON Cross Reference NMS256 256K RAM HM62256 MK6264 51256SL TC5565 "cross reference" MN44256 M5M5256
Contextual Info: Static RAM Cross Reference STATIC RAM CROSS REFERENCE ORGANIZATIONAL STRUCTURE 2K 2K X X 32K 8K X e w/CE, OE 8 W/CE1, CE2 X 8 Stow 8 Slow COMPETITIVE VENDOR SH ARP MODEL LH5116 LH5118 LH51256 LH5164A AMD Am9128 Harris CDM6116 Hitachi HM6116A Hyundai HY6116

LH5911

Abstract: lh5167-55 LH5101 LH52250 LH5160D LH5167 LH52252 LH5114H lh5160n 4kx8 static ram ttl
Contextual Info: NOV 0 5 1990 L H 5 9 1 1 /L H 5 9 1 2 /L H 5 9 1 4 2K x 8 CMOS Dual Port RAM Preliminary Data Sheet Functional Description Features The LH5911. LH5912 and LH5914are dual port static RAMs that use true dual port memory cells to allow each port to independently access any location in memory.

lh5168

Contextual Info: MEMORIES Static RAMs ★ Under development P ro ce ss C a p a c ity C o n fig u ra tio n Model No. A c c e s s tim e n s 70 80 90 100 120 LH5116 2k X 8 16k LH51116H Operating temperature : - 40 to 8 5 t IUUU "O LH5116S Supply voltage : 3 V±10% LH5168 Full

5268A

Abstract: 28-SOP LH521002AK-2S 28SOP LH52256CVN
Contextual Info: MEMORIES S tatic RAMs Process Capacity Configuation words Xbits 2k 16k 8 X Access time Supply current ns) MAX. Cycle time Operating, Standby (ns) MIN. !mA) MAX. (mA) MAX. Model No. Supply Operating voltage temp. 0C) m i i LH 5116/NA/D-10 100 40 0.001 5 ± 10%

LH521007AK-20

Contextual Info: STATIC RAM ☆ New product ★ Under development STATIC RAMs ♦ Features • The product lineup includes a wide variety of bit configurations x4, x8, x l6 , x l8 , x32 . • High-speed synchronous devices for the secondary cache memory are available for use with low-voltage, lowpower CPUs idpal for portable equipment.

LHS168

Abstract: LH52252A LH52252
Contextual Info: V .J 1 íVt! Static RAMs ★Under development Process Capacity Model No. Configuration Access time ns 70 -I 16k 2k Package 90 100 120 LH5116 J— I. 24 24 24 LH5116H 3 -T 24 24 24 - Z ÏÏ-J 1 24 24 24 C E , C S c o n tro l Data retention current : 0.2 pAjMAXj j

SXX12

Contextual Info: CMOS 64K x 18 Static RAM FEATURES • Fast Access Times: 20/25/35 ns • Wide Word 18-Bits for: - Improved Performance - Reduced Component Count - Nine-bit Byte for Parity • Transparent Address Latch • Reduced Loading on Address Bus • Low-Power Stand-by Mode when

IR2E27A

Abstract: IR2C53 IR2E02 IR2E27 IR2E10 IR3N34 IR2E31A IR2E01 IR2C07 ir2e31
Contextual Info: lndeX Model No. ARM7D CPU Core28,32,33 ARM7DM 28,33 CMOS CMOS CMOS CMOS 76 5A A F G 44 44 44 44 ID1 series ID2 series ID3 seríes ID21K064 ID21K128 ID21K256 ID21K512 ID21M010 ID21M015 ID21M020 ID21M040 ID22K256 ID22K512 ID22M010 ID22M020 ID22M040 ID22M080

Contextual Info: L H 521 0 2 8A CMOS 64K x 18 Static RAM FEATURES • Fast Access Times: 15/17/20/25/35 ns • Wide Word 18-Bits for: - Improved Performance - Reduced Component Count - Nine-bit Byte for Parity andSu are also usedtoenable or disable Read and Write operations on the high and the low bytes. The Address

100 10L AD

Abstract: LH521007AK-25 LH5168ST LH5168SHN lh5168 LH521002AK20
Contextual Info: MEMORIES • S ta tic R A M s Process Capacity ★ U nderdevelopm ent Configuration words Xbits Model No. Access tim e Supply current (ns) MAX. Cycle time operating/standby ImA) MAX. (ns) MIN. Supply voltage (V) Operating temperature (1C) Package LH5116/NA/D-10