HD74S Search Results

Contextual Info: HD74SSTL16857 14-bit SSTL_2 Registered Buffer HITACHI ADE-205-223B Z Preliminary 3rd. Edition February 1999 Description The HD74SSTL16857 is a 14-bit registered buffer designed for 2.3 V to 3.6 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.

HD74SSTV16857

Abstract: HD74SSTV16857NEL HD74SSTV16857TEL TSSOP-48
Contextual Info: HD74SSTV16857 1:1 14-bit SSTL_2 Registered Buffer REJ03D0830-0700 Previous: ADE-205-336F Rev.7.00 Apr 07, 2006 Description The HD74SSTV16857 is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.

HD74SSTV16857A

Abstract: HD74SSTV16857ANEL HD74SSTV16857ATEL TSSOP-48
Contextual Info: HD74SSTV16857A 1:1 14-bit SSTL_2 Registered Buffer REJ03D0831-0100 Previous: ADE-205-695 Rev.1.00 Apr 07, 2006 Description The HD74SSTV16857A is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.

Y8A transistor

Abstract: HD74SSTV16842
Contextual Info: HD74SSTV16842 11–bit to 22–bit Buffer with SSTL_2 Inputs and Outputs REJ03D0829-0200 Previous: ADE-205-602A Rev.2.00 Apr 07, 2006 Description The HD74SSTV16842 is a 11–bit to 22–bit buffer designed for 2.3 V to 2.7 V Vcc operation and SSTL_2 data (A)

HD74SSTV16857B

Abstract: HD74SSTV16857BNEL HD74SSTV16857BTEL TSSOP-48
Contextual Info: HD74SSTV16857B 1:1 14-bit SSTL_2 Registered Buffer REJ03D0023–0100Z Previous ADE-205-712 (Z Rev.1.00 Jun.03.2003 Description The HD74SSTV16857B is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.

Hitachi DSA002752

Contextual Info: HD74SSTL16857 a 14-bit SSTL_2 Registered Buffer ADE-205-223C Z 4th. Edition May 1999 Description The HD74SSTL16857 is a 14-bit registered buffer designed for 2.3 V to 3.6 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.

Hitachi DSA002785

Contextual Info: HD74SSTV16842 11–bit to 22–bit Buffer with SSTL_2 Inputs and Outputs ADE-205-602 Z Preliminary 1st. Edition March 2001 Description The HD74SSTV16842 is a 11–bit to 22–bit buffer designed for 2.3 V to 2.7 V Vcc operation and SSTL_2 data (A) inputs.

HD74SSTV16859

Abstract: Q11A DSA003634
Contextual Info: HD74SSTV16859 1:2 13-bit SSTL_2 Registered Buffer ADE-205-337G Z Rev.7 June 2001 Description The HD74SSTV16859 is a 1:2 13-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.

Contextual Info: HD74SSTL16837 20-bit SSTL_3 Interface Universal Bus Driver with 3-state Outputs HITACHI ADE-205-191 Z Preliminary 1st. Edition July 1, 1997 Description The HD74SSTL16837 is a 20-bit universal bus driver designed for 3.0 V to 3.6 V Vcc operation and SSTL_3 or LVTTL I/O levels.

LK 1628

Abstract: HD74SSTV32852 HD74SSTV32852LBEL Q13A BP-114
Contextual Info: HD74SSTV32852 24-bit to 48-bit Registered Buffer with SSTL_2 Inputs and Outputs REJ03D0833-0400 Previous: ADE-205-687C Rev.4.00 Apr 07, 2006 Description The HD74SSTV32852 is a 24-bit to 48-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS

TTP-64DV

Contextual Info: HD74SSTV16842 11–bit to 22–bit Buffer with SSTL_2 Inputs and Outputs REJ03D0829-0200 Previous: ADE-205-602A Rev.2.00 Apr 07, 2006 Description The HD74SSTV16842 is a 11–bit to 22–bit buffer designed for 2.3 V to 2.7 V Vcc operation and SSTL_2 data (A)

16-LINE TO 4-LINE PRIORITY ENCODERS

Abstract: 74 series logic gates Flip flops "J-K Flip flops" J-K Flip flops NAND Gates HD74 Synchronous 8-Bit Binary Counters HD74S synchronous binary counter with latch
Contextual Info: o V o la i \ \_ a . TTL H D 74/H D 74S Series I M A IN C HARACTERISTICS I PERFORMANCE (per gate Performance HD74 Series HD74S Series Propagation 10 ns 3 ns Delay Time Power 10 mW 20 m\V Dissipation Speed-Power 100 pJ 60 pJ Product O Series Param eter max)

4-bit bidirectional shift register 74 194

Abstract: 16-LINE TO 4-LINE PRIORITY ENCODERS 74 series logic gates 4-bit even parity checker J-K Flip flops 4-bit shift register 74 194 Flip Flops HD74 H183 74 series 7 segment decoders
Contextual Info: O o TTL HD74/HD74S Series I M AIN C H A R A C T E R IS T IC S Ta = - 2 0 - + 75° C I P E R F O R M A N C E (per gate) H D 74 S e r ie s P e rfo rm a n c e P r o p a g a t io n 10 ns D e la y T im e P a ra m e te r 3 ns V Pow er D is s ip a t io n 10 m W

Contextual Info: HD74SSTV16859 1:2 13-bit SSTL_2 Registered Buffer REJ03D0832-0900 Previous: ADE-205-337H Rev.9.00 Apr 07, 2006 Description The HD74SSTV16859 is a 1:2 13-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.

HD74SSTV16859

Abstract: Q11A Hitachi DSA00219
Contextual Info: HD74SSTV16859 1:2 13-bit SSTL_2 Registered Buffer ADE-205-337F Z 7th. Edition January 2001 Description The HD74SSTV16859 is a 1:2 13-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.

Contextual Info: HD74SSTV16857A 1:1 14-bit SSTL_2 Registered Buffer REJ03D0831-0100 Previous: ADE-205-695 Rev.1.00 Apr 07, 2006 Description The HD74SSTV16857A is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.

Contextual Info: HD74SSTV16857 1:1 14-bit SSTL_2 Registered Buffer REJ03D0830-0700 Previous: ADE-205-336F Rev.7.00 Apr 07, 2006 Description The HD74SSTV16857 is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.

Hitachi DSA002744

Contextual Info: HD74SSTL16857 14-bit SSTL_2 Registered Buffer ADE-205-223B Z Preliminary 3rd. Edition February 1999 Description The HD74SSTL16857 is a 14-bit registered buffer designed for 2.3 V to 3.6 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.

HD74SSTV16857

Abstract: TSSOP-48 DSA003634
Contextual Info: HD74SSTV16857 1:1 14-bit SSTL_2 Registered Buffer ADE-205-336F Z Rev.6 June. 2001 Description The HD74SSTV16857 is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.

HD74SSTV16842

Abstract: DSA003635
Contextual Info: HD74SSTV16842 11–bit to 22–bit Buffer with SSTL_2 Inputs and Outputs ADE-205-602A Z Rev.1 May 2001 Description The HD74SSTV16842 is a 11–bit to 22–bit buffer designed for 2.3 V to 2.7 V Vcc operation and SSTL_2 data (A) inputs. Features • Supports SSTL_2 data inputs

Contextual Info: HD74SSTL16857 14-bit SSTL_2 Registered Buffer HITACHI ADE-205-223 Z Preliminary 1st. Edition August 1998 Description The HD74SSTL16857 is a 14-bit registered buffer designed for 2.3 V to 3.6 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and output levels.

HD74SSTV16857A

Abstract: TSSOP-48 Hitachi DSA0047
Contextual Info: HD74SSTV16857A 1:1 14-bit SSTL_2 Registered Buffer ADE-205-695 Z Rev.0 Jun. 2002 Description The HD74SSTV16857A is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.

HD74SSTV16857BNEL

Abstract: HD74SSTV16857B HD74SSTV16857BTEL TSSOP-48
Contextual Info: HD74SSTV16857B 1:1 14-bit SSTL_2 Registered Buffer REJ03D0023–0100Z Previous ADE-205-712 (Z Rev.1.00 Jun.03.2003 Description The HD74SSTV16857B is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.

Flip Flops

Abstract: 74 series logic gates DP-14 H183 HD74 2 input nand gate 24v 74 series 7 segment decoders quad jk flip flop
Contextual Info: TTL HD74/HD74S Series • PER FO RM A N C E per gate P erform an ce Propagation D elay T im e P o w er D issip atio n S p ee d -P o w e r P roduct B M A IN C H A R A C T E R IS T IC S (7 > - 2 0 — + 7 5 cC) H D 74 S e r ie s H D 7 4 S S e r ie s 10 ns